Vybrid Cortex-M4 Bare Metal L1 Data Cache disable and enable

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Vybrid Cortex-M4 Bare Metal L1 Data Cache disable and enable

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Contributor III

When using Vybrid Cortex-M4 bare metal debug, can L1 data cache being disabled? where should I change the setting?

And here're two questions, what's the data cache and instruction cache miss penalty in Systicks ?

Is Systick equals to cycle? Because I measured instruction NOP, it takes 6 systicks

Thanks,

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Community Manager
This an automatic process.

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Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

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Senior Contributor II

Hi,

You can find more about vybrid cortex-M4 cache operation (enable/disable) in "MQX_4_1_1_LINUX_GA/mqx/source/psp/cortex_m/cache.c" with the help of "MQX_User_Guide.pdf" reference manual in MQX_4_1_1_LINUX_GA/doc/mqx.

To enable/access the data cache, need to enable MMC, which is discussed in below thread:

https://community.nxp.com/thread/315672

Thanks,

Timesys Support

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NXP Apps Support
NXP Apps Support

timesyssupport​ can you help to review this case?

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