When using Vybrid Cortex-M4 bare metal debug, can L1 data cache being disabled? where should I change the setting?
And here're two questions, what's the data cache and instruction cache miss penalty in Systicks ?
Is Systick equals to cycle? Because I measured instruction NOP, it takes 6 systicks
Solved! Go to Solution.
You can find more about vybrid cortex-M4 cache operation (enable/disable) in "MQX_4_1_1_LINUX_GA/mqx/source/psp/cortex_m/cache.c" with the help of "MQX_User_Guide.pdf" reference manual in MQX_4_1_1_LINUX_GA/doc/mqx.
To enable/access the data cache, need to enable MMC, which is discussed in below thread: