VF5xx/LPSTOPx mode

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VF5xx/LPSTOPx mode

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Contributor IV

Hello,

Q1)

Please tell me the method to hold data of DDR3 or LPDDR2 in LPSTOPx mode.

Q2)

Please tell me the method to hold data of the internal RAM in LPSTOPx mode.

Best regards,

soichi yamamoto

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Senior Contributor V

Dear Soichi,

  • The below text is to be added into our future Vybrid Tower board documentation:

Note regarding DDR3 Self-Refresh mode when Vybrid in LPStop modes:

* Not supported - as per Datasheet, DDR_RESET and  DDR_CKE pins are in High-Z state in these modes.

* To add such support, following board modifications required:

1. Depopulate R107,

2. Add 10K pull-up to VCC_1V5 rail on DDR_RESET net,

3. Add 10K pull-down to GND rail on DDR_CKE net.

  • In this modes, only part of the memory contents can be retained - it is a good compromise to keep power consumption low.

Regards, Naoum Gitnik.

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Contributor IV

Dear Naoum, Does IOConfiguration maintain it  in LPSTOPx mode.? Best Regards, soichi yamamoto

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Senior Contributor V

Dear Soichi,

Unfortunately, Vybrid is designed so that the pins' states are not controlled/retained in the LPStop modes; this is why external resistors are required (otherwise I would recommend you relevant settings...).

Regards, Naoum Gitnik.

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Contributor IV

Dear Naoum, Thank you for reply. Please tell me states of pin in LPStop modes? input or output? states of WKPU Pin ? Best regards, soichi

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Senior Contributor V

"Dear Soichi,

  1. As per the Datasheet, DDR_RESET and  DDR_CKE pins are in High-Z state in these modes.
  2. I am having difficulties understanding how the WKPU feature is related to DDR... but, according to the Reference Manual, '8.4.1 WKPU configuration' - "The table below [Table 8-4. WKUP Pins] shows the internal and external inputs to the WKUP module supported by the device.

Regards, Naoum Gitnik.

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Contributor IV

Dear Naoum, Please tell me about the status of IO except the DDR. Best Regards, soich,

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Senior Contributor V

Dear Soichi,

This information is in the "14.3 Low-power modes" section, in "Table 14-2. Power gating and clock gating overview".

Briefly, they are in the High-Z state (the WKUP ones described separately, as I mentioned earlier - also see "14.3.7 Interrupt connectivity").

All the idea of LPSTOP modes is to save as much power as possible (this is why they are called "power-gating"), so a lot of power domains on the die are simply "powered off".

Regards, Naoum Gitnik.

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Contributor IV

Dear Naoum,

Thank you for reply.

What is High-Z state?

Which Is IO Input or output?

Which Is Logic High or Low?

Best Regards,

soichi

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Senior Contributor V

Dear Soichi,

The definition is here - High impedance - Wikipedia, the free encyclopedia.

Regards, Naoum Gitnik.

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Contributor IV

Dear Naoum,

Thank you for reply.

Is Default of Kintis Pin same as High-Z state?

Best Regards,

soichi

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NXP Employee
NXP Employee

Hi Soichi,

The default for most Kinetis pins are to be tri-stated out of reset.

Regards,

Juan

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NXP Apps Support
NXP Apps Support

naoumgitnik please continue with the follow up on this case.

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