VF5xx/LPSTOPx mode for LPDDR2 and IO.

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VF5xx/LPSTOPx mode for LPDDR2 and IO.

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soichiyamamoto
Contributor V

Hello,

I use LPDDR2.

Q1) Please tell me the method to hold data of LPDDR2 in LPSTOPx mode.

Q2)LPDDR2 has the main program and runs.

And  Go to LPSTOPx mode,

Please tell me the state transition procedure to LPSTOPx mode.

Q3) What happens to Peripheral register in LPSTOPx mode?

Best Regards,

soichi

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naoumgitnik
Senior Contributor V

Dear  Soichi,

  • You have to keep the power rails alive for the pull-ups/downs involved in the DDR Self-Refresh and Wakeup, right? To lower the leakage, you may use higher-resistance pull-ups/downs, e.g. of the same order of magnitude as the Vybrid's built-in ones.
  • For the rest of IOs, you have all the freedom to save power if required.

Regards, Naoum Gitnik.

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juangutierrez
NXP Employee
NXP Employee

Regarding Q3

According to Table 14-2. Power gating and clock gating overview in RM

All clocks to the peripherals are gated by the CCM. All Peripherals are off (power-gated) except for those modules in the Power Domain (PD1) like LPTimer, SRC, VREG_DIG, GPC, WKPU, PMU, FIRC, ADC0, ADC1, LCD, 17 GPIO pads for wakeup

Regarding Q2

You can check the entry sequence in Section 14.3.6.1 LPStopn mode entry sequence (power-gating mode) of RM

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soichiyamamoto
Contributor V

Dear Juan,

Thank you for reply.

It is a question about an answer to Regarding Q2.

I want to perform the intermittent movement such as follows.
 LPStopn -> RUN -> LPStopn -> Please tell me the sequence.

    The condition, When a program works in LPDDR2 and shifts to LPSTOP mode.

1.In the case from RUN to LPSTOP mode.

・Is it the maintenance method of the program?
・When a program works in LPDDR2, can you shift to LPSTOP mode?

2. In the case from LPSTOP to RUN mode

・Do you come by mode transition?
・What happens at the time of the return at RUN mode time?
・LPSTOP mode->At the time of RUN state transition  Is the return possible for a program of LPDDR2?


It is a question about an answer to Regarding Q3.

・Is DDRMC Peripheral data hold in LPSTOP mode?

・If not hold, Do the LPDDR2 data not have what is not maintained? To set DDRMC again.

・Is IOMUXC Peripheral data hold in LPSTOP mode?


Best Regards,

soichi

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naoumgitnik
Senior Contributor V

Juan Antonio Gutierrez Rosas, may you take a look, please?

Thanks in advance, Naoum Gitnik.

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karina_valencia
NXP Apps Support
NXP Apps Support

juangutierrez do you have an update on this case?

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juangutierrez
NXP Employee
NXP Employee

No much experience with LPDDR2 and Power Managment. I think this is a generic question regarding LPDDR2 and PM so maybe somebody else can with more experienced in this can be pulled.

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karina_valencia
NXP Apps Support
NXP Apps Support

naoumgitnik can you  investigate about it  to provide follow up?

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soichiyamamoto
Contributor V

Hi,

Following is my assumption. Could you please give me your comments?

In LPSTOPx mode, internal SRAM can hold data, also LPDDR2 can be self-refresh mode by pulling down CKE.

But Vybrid PD1 power domain will be cut, so most of Vybrid internal register contents will be lost.

DRAM_MC and IOMUXC are in PD1 domain(RM Table 14-1), these register contents will also be lost.

To resume from LPSTOP mode, Vybrid SRC will issue reset. This is the only way to resume from LPSTOPx.

SRAM contents are kept here, it will help shortening boot sequence period.

For LPDDR2, DRAM_MC register contents can be loaded from SRAM,

but DRAM_CR00[START] bit should be set to start DRAM controller.

Asserting DRAM_CR00[START] bit will also issue LPDDR2 initialization sequence automatically.

If LPDDR2 is initialized, contents are not guaranteed, means LPDDR2 contents will be lost.

If my understanding is correct, following 3 will be the summary.

    Only internal SRAM can be available if we want to keep contents after LPSTOP mode.

    LPDDR2 must be re-initialized after LPSTOP mode

    IOMUXC must be re-initialized after LPSTOP mode

Best Regards,

soichi

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naoumgitnik
Senior Contributor V

Dear Soichi,

Sorry for delayed reply.

Yes, your conclusions are correct, with some minor comments below:

  • Only internal SRAM can be available if we want to keep (retain) contents after LPSTOP mode.

- Correct for LPStop2 and LPStop3 (not LPStop1), and take into account there is no way to retain all the SRAM data - only 16K for LPStop2 and 64K for LPStop3 (see ‘14.3.6 LPStopn modes’ section of the Reference Manual).

- In addition - as we already discussed earlier, there is a way to retain DDR data in its Self-Referesh mode, but with DDR in it, Vybrid is unable to read anything from it, meaning executing from DDR in this situation is impossible, only from SRAM.


  • LPDDR2 must be re-initialized after LPSTOP mode

Correct, but I would rather call it 'take out of Self-Referesh'.

  • IOMUXC must be re-initialized after LPSTOP mode.

Correct, but I would rather call it 're-configure'.

Sincerely, Naoum Gitnik.

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soichiyamamoto
Contributor V

Dear Naoum,

Thank you for reply.

I'd like to ask questions about the following matters.

> ・IOMUXC must be re-initialized after LPSTOP mode.

>    Correct, but I would rather call it 're-configure'.

It is a help about the port processing except the wakeup pin in LPSTOP3.


Because the port processing except the Wakeup pin has many pulling up ports, I worry about a leak current to MPU.

Q1)About IO except the Wakeup pin, should I do coping of the leak current for the voltage from the outside?

Q2) Could you please suggest how I deal with this matter?

Best regards,

soichi

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naoumgitnik
Senior Contributor V

Dear  Soichi,

  • You have to keep the power rails alive for the pull-ups/downs involved in the DDR Self-Refresh and Wakeup, right? To lower the leakage, you may use higher-resistance pull-ups/downs, e.g. of the same order of magnitude as the Vybrid's built-in ones.
  • For the rest of IOs, you have all the freedom to save power if required.

Regards, Naoum Gitnik.

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naoumgitnik
Senior Contributor V

Dear  Soichi,

To find answer for your "hold data" question, please, find information for the LPRRD2 chip you are using in your design, specifically for its "Self-Refresh" mode - what states are required for the pins involved in this mode. Since most likely these pins on the Vybrid side are in the high-impedance state in the LPStop modes, you will have to use external pull-up/down resistors, similarly to how it is shown for DDR3 in our reference design.

juangutierrez, may you comment on the other 2 questions, please?

Regards, Naoum Gitnik.

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soichiyamamoto
Contributor V

Dear Naoum, Thank you for relpy. hold data is main program at 10MB~100MB. Please give me Spec  of "Self-Refresh" mode for LPDDR2. Best Regards, soichi

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naoumgitnik
Senior Contributor V

Dear  Soichi,

Let me somewhat repharse my last reply.

You are the only person who knows what LPRRD2 chip type you are using in your design. In its datasheet, find information about the "Self-Refresh" mode - what states are required for the pins involved in this mode.

Since most likely these pins on the Vybrid side are in the high-impedance state in the LPStop modes, you will have to use external pull-up/down resistors, similarly to how it is shown for DDR3 in our reference design.

Regards, Naoum Gitnik.

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