Using PLL5 for RMII-Clock

slw · ‎02-02-2014

Hi,

I have a custom board with a PVF522R and a Ethernet-PHY using RMII.

I want to use the PLL5 as clock source for the internal MAC and the PHY (PTA6 / RMII_CLOKOUT).

First tests shown that data from Phy to MAC is working well, but data-transfer from MAC to PHY is not stable.

It seams that therre is something wrong with my settings cause the MAC puts data on the RMII on the falling edge of the RMII-Clock, not on the rising edge.

When I use a external clock for RMII and set PTA to RMII_CLKIN all works fine.

Any suggestions?

Or is there a problem cause the controller is a engineering sample ?

Regards

naoumgitnik · ‎04-10-2014

Dear Sebastian,

I am glad my last, the better workaround works quite well for you; you have to be sure, though, the RMII spec timing requirements are met, and not just marginally.

I am still working with our Vybrid IC design team to verify if there is a way to add a delay in to the clock or data signals directly, not just playing with the pulse slope; their first, unofficial, reaction is that such option does NOT exist, and we have to apply workarounds for it (will let you know if their official reply differs, but it is quite unlikely…).

So, it looks like the summary is to use 3 possible workarounds to fix the timing:

1. Which you already proved - using an additional Vybrid IO to output 50MHz clock to be used by both Vybrid PTA6 pins and the PHY (IMO, the most straightforward one),

2. Inverting the RMII clock with an additional external inverter (is the RMII spec timing met then?),

3. Playing with the TX Data pulse slope (equivalent to inserting artificial delay) - not sure if you may always count on the parasitic capacitance (PHY input + PCB stray), might need to add external capacitors to keep it spec-compliant for all voltage-temperature-process variations.

Thanks a lot in helping us find and resolve this issue!

Sincerely, Naoum Gitnik.

View solution in original post

naoumgitnik · ‎02-07-2014

Dear Timesys Support,

Unfortunately, settings for the Vybrid Tower board are irrelevant in this case - Vybrid on this board uses external RMII Ethernet clock.

Relevant is the Vybrid Automotive (a.k.a. Auto) board, on which Vybrid provides clock for an Ethernet PHY (please, see my oroginal information).

Do you have code for it, please?

Sincerely, Naoum Gitnik.

slw · ‎02-10-2014

Hi Naoum,

The uboot-package above includes sources for the Vybrid Tower and the AutoEVB and

I have compared my own settings to the settings of the AutoEVB. But without success (see my posting from 07.02.2014)

Do you have a AutoEVB to make a measurement of the RMII-Clock and the TX-lines ?

Is there an difference between the engineering samples and the series production concerning the RMII-interface ?

Regards Sebastian

naoumgitnik · ‎02-11-2014

Dear Sebastian,

As of now, I do not really have an Auto EVB on-hand to connect a scope to it, and before starting building and running this test setup (involving other people as well), I'd like to first understand what new we are expecting to see during this test.

The major point here is that the Ethernet PHY used on it (see datasheet attached) requires the same clock/data timing (data sampled on clock's rising edge) as yours, right? - Since both of them are based on the same RMII specification.

I am not a SW person, but is it possible to run our Auto EVB code on your board, even though some part of the IOs will be configured inappropriately for your board? - At least the Ethernet section will be configured fully identically to how it is on the Auto EVB.

Sincerely, Naoum Gitnik.

slw · ‎02-19-2014

Dear Naoum,

Its not so easy to get the AutoEVB-Board running on our custom board.

I will try to get a AutoEVB-board from our official freescale-sales-partner to do further tests.

When there are some new results I'm gonna tell you.

Regards Sebastian

Using PLL5 for RMII-Clock

Using PLL5 for RMII-Clock

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