Tower board low power chz

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Tower board low power chz

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Contributor III

I'll be running some low power scenarios on the Vybrid Tower board and would like to get some input.  What are some of the most common use cases?

For example:

- Run from DDR, jump to SRAM (DDR in self refresh), enter LPRUN, run functional code, exit LPRUN, exit DDR self-refresh, jump back to DDR running at full speed (396 MHz).   Then you can throw in whether the M4 is running or not during this flow.

The low power modes available are:

- LPRUN

- ULPRUN

- WAIT

- STOP

- LPSTOP1,2,3

I'd like feedback on the top 3 use cases/configurations that we'd like to demonstrate.  Any/All feedback is appreciated!

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NXP Employee
NXP Employee

Hi David,

Good topic and thanks for asking for input.

One Senario

- A5 doing the highend graphics and interactive stuff...audio too..while M4 purring along doing status and control.  Now when task/job complete or no more user input activity, then A5 to lower power, M4 can handle inactive display and wait for wakeup and potentially reduce its frequency and/or go into VLPR operation (and VLPW when noting to do).  User activity wakes up the system (timer or HMI or serial or network).

Regards,

David