Request for Clarification on SPI clk

[n00b1024]

Hello,

I'm working with SPI on the VF60 (Vybrid), and am trying to find out the max frequency that the SPI can run at. According to the RM, the maximum SPI clock frequency is half the system clock (spi_clk = sys_clk*(1+DBR)/(PBR*BR), where DBR = 1, PBR = 2, BR = 2, cf. Section 47.4.3, Vybrid Reference Manual rev5). When the RM talks about the "system clock," what is it referring to? Is that the IPS clock frequency, or the Platform Bus clock? There's a note on page 630 (Sec 9.12) that says that the max baud rate for the SPI output is 83 MHz.

Also, Table 9-10 says that the max IPG (output) frequency is 85 MHz, while Table 9-5 says that the max IPG frequency is 83 MHz.

Thanks much!

[naoumgitnik]

Dear n00b1024,

1.

According to the RM section 10.2.3, the "SYS_CLK_SEL" (System clock select) has several source options:

• 000 Fast clock o/p defined by CCM_CCSR[FAST_CLK_SEL]
• 001 Slow clock o/p defined by CCM_CCSR[SLOW_CLK_SEL]
• 010 PLL2 PFD o/p clock defined by CCM_CCSR[PLL2_PFD_CLK_SEL]
• 011 PLL2 main clock
• 100 PLL1 PFD o/p clock defined by CCM_CCSR[PLL1_PFD_CLK_SEL]
• 101 PLL3 main clock

2.

Regarding the maximum SPI clock frequency:

I am a bit confused - you wrote "There's a note on page 630 (Sec 9.12) that says that the max baud rate for the SPI output is 83 MHz.", does it answer your question, please?

3.

Regarding the maximum IPG clock frequency ("Table 9-10 says that the max IPG (output) frequency is 85 MHz, while Table 9-5 says that the max IPG frequency is 83 MHz."):

Indeed, somewhat confusing; if we were being conservative and going for 83 (not 85) MHz, would that be critical for your design, please?

Sincerely, Naoum Gitnik.