Good point, Bill!
"7.3.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled.
The Port Data Input registers return the synchronized pin state after any enabled digital filter in the Port Control and Interrupt module. The input pin synchronizers are shared with the Port Control and Interrupt module, so that if the corresponding Port Control and
Interrupt module is disabled, then synchronizers are also disabled."
Interestingly enough, "This config works OK with the two switches GPIO on the Tower VyBrid board" for the discussion originator; IMO, something changed in the settings, and quite likely what you mentioned.
Regards, Naoum Gitnik.