QuadSPI0 cacheable write-back

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QuadSPI0 cacheable write-back

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eugeneryabtsev
Contributor III

According to page 1158 of Vybrid Reference Manual (F-Series; VYBRIDRM Rev 7, 06/2014), memory range from 0x20000000 to 0x2FFFFFFF is QuadSPI0 and "cacheable write-back".

My question is: "write-back" to what? Probably not to flash. Can we put some ferromagnetic memory in there and work with it just like with normal memory, but non-volatile? Where do I read more about this kind of setup? Are there any examples?

Or is does this mean something else?

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alejandrolozan1
NXP Employee
NXP Employee

ARM defines that region in the Cortex M4 as executable and with cache write back attribute.

You can copy code there and execute it.

The next AppNote explains the QSPI module.

Best Regards,

Alejnadro

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eugeneryabtsev
Contributor III

Our chip does not have the M core. We only use A5. Anyway, whe next chapter starts by saying that "The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to one single or two external serial flash devices...", with "flash" in every other sentence throughout the chapter. This probably means that either:

1. Non-flash devices are not going to work

or

2. The doc is incomplete

Which is it?

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alejandrolozan1
NXP Employee
NXP Employee

QSPI NOR Flash work for the Cortex-A5 too. Why it should not work?

/Alejandro

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eugeneryabtsev
Contributor III

It works just fine, but it is not easily write-able without some procedure. I wonder if some QSPI FRAM or something can be WRITE-mapped into QSPI window. The doc says a lot about Flash, but not a lot about any other types of memory.

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