Pin FMEA of Vybrid

cancel
Showing results for 
Search instead for 
Did you mean: 

Pin FMEA of Vybrid

Jump to solution
392 Views
Contributor III

Dear community.

Our customer has question below.

1, In power supply group, Pin Out single use only of the terminal (below exported terminal)
Would you please tell me the operation at the time of open failure.

V14  VBAT
T12  VDD33_LDOIN
P5  VDDREG
V1  VDDA33_ADC
W1  VREFH_ADC
V3  VDDA33_AFE
T5  VDD12_AFE
N7  FA_VDD
W11  USB0_VBUS
U9  USB1_VBUS

2, Terminals mulch function is allocated to a number pins
      ex. VDD33 K3 ~ W18
There are connected K3 ~ W18 is all on the internal BGA in the PCB( sub strate)?

Similarly, SDRAMC_VDD1P5, VDD, SDRAMC_VDD2P5, will also answer please.

3, would you please tell us about the behavior of each failure mode of the following terminal .

P5   VDDREG            OPEN failure and, please tell us about the function and use of this terminal.
T5   VDD12_AFE        GND Short.
T12  VDD33_LDOIN      Short of a T11 DECAPV25.
W2  ADC0SE9              OPEN failure and GND short, please tell us about the function and use of this terminal.
W14 LVDS0P                 3.3V  short, and GND short, please tell us about the function and use of this terminal.

Labels (1)
0 Kudos
1 Solution
163 Views
Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

0 Kudos
2 Replies
164 Views
Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

0 Kudos
164 Views
NXP TechSupport
NXP TechSupport

Hi Takashi

all publicly available information and documentation is located on Vybrid product page

VF5xxR ARM Cortex A5/M4 MPUs|Vybrid|NXP

All other info related to internal chip organization and failure behaviours

is considered as confidential and may be provided using contact with

local marketing office (NDA may be required).

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

0 Kudos