My understanding is that only those commands that require up to 3 address cycles will be executed, and the rest of the commands (that require more than 3 address cycles) will be impossible to be executed
I think we should discourage the use of 4 and 5 address cycles NAND flashes for Vybrid
My understanding is that only those commands that require up to 3 address cycles will be executed, and the rest of the commands (that require more than 3 address cycles) will be impossible to be executed
I think we should discourage the use of 4 and 5 address cycles NAND flashes for Vybrid