MVF61NN151CMK50 maximum FlexTimer clock frequency (what the system clock is)?

[os-freescale-co]

Hi,

I am going to use FTM capture mode for period measurement. Looking into the datasheet (VYBRIDRM.pdf), possible FTM clocks are: system clock, fixed frequency clock, external clock. I have not found a direct description of what the "system clock" is for FTM. I assumed that it is the System Core Clock for A5, that is, around 396MHz or so. But sample code showed that the real clock is only 66MHz (while A5 clocked at 396MHz). PDF references for other CPUs with FlexTimer explicitly tell that "FTM system closk is the bus clock, around 66MHz", but VYBRIDRM.pdf does not explain this (or I missed that). At the same time the table 9-10 (page 628) introduces "flex_root_clk" clock name, for which the maximum frequency is 85MHz. This flex_root_clk is found in the document just once, and no more references to it. It looks like FTM clock = Bus clock.

So my questions are:

1. What is the maximum frequency for FTM clock of MVF61NN151CMK50?
2. What the "system clock" for FTM is?
3. Where it is documented for this chip?

Thanks!

[CommunityBot · Accepted solution]

This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

[alejandrolozan1]

Hi,

The clocking of FTM is shown below:

FTM has options for Fixed clock, System clock, and External clock. The system clock is fixed at IPG_Clk divided by 2, so is 83 MHz is the IPG clock (or CM4 ) is running at 167MHz. All other clocks have to follow the relation as stated in the Reference Manual. I am quoting them again below:

• The fixed frequency clock is an alternative clock source for the FTM counter that allows the selection of a clock other than the system clock or an external clock. This clock input is defined by chip integration.
• Due to the FTM hardware implementation limitations, the fixed frequency clock frequency must not exceed 1/2 of the system clock frequency.
• The frequency of the external clock source must not exceed 1/4 of the system clock frequency.

As far as the IO speed is concerned, I don't think the IO's will have a problem propagating a 42MHz signal (half of 83 MHz).

Best Regards,

Alejandro

[dry]

> The system clock is fixed at IPG_Clk divided by 2, so is 83 MHz is the IPG clock (or CM4 ) is running at 167MHz

Shoudn't this be IPG clock = Platform Bus or CM4 Clock / 2?    (Table 6-6 Clocking Configuration).

And then the undefined 'system clock' in the manual is actually = IPG clock, not IPG / 2.

[os-freescale-co]

Thank you for the answer.

It seems to be correct, but FTM clocking diagram does NOT show "system clock". So could you please point me to the statement in a document where "The system clock is fixed at IPG_Clk divided by 2" is written? I did not find it so asked the question. Or, if it is not documented, then would be good to have it finally fixed in the manual. Still, I believe that I missed that.