Hi Naoum,
Yes, in the "MSCM memory map" table (on page 3394 & cont.) all the registers are mentioned. However, according to the table, the chapter e.g. 64.3.8 should describe 4 registers. However, that chapter only contains the first chapter.
Click for instance on "MSCM_CPxCFG1".It jumps to the chapter 64.3.8 called MSCM_CPxCFGx, but in there only the first register (MSCM_CPxCFG0) is described. Just after that, the MSCM_CP0TYPE follows.
In the Rev. 5 manual, after MSCM_CPxCFG0 followed the description of MSCM_CPxCFG1 (which contain the Level 2 cache information for instance)... This is missing in the Rev. 7 manual.
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Stefan