Is it possible to share the data structure between two cores A5 & M4 core in vybrid processor?

[karthigeyannata]

We are working on the software development using vybrid processor. We are analyzing efficient way for data exchange between A5 and M4 core. We have data structure which contains variables of all the types (bool, int, short int etc). We would like to keep this structure in the shared memory and access the same structure in both A5 and M4 core. We are worried that the size of the structure might vary between A5 and M4 core since it is entirely 2 different cores.If the size differes due to structure alignment/padding , then this mechanism will not work

Please advise on this

[kubiznak_petr]

Hi Karthigeyan,

for the case of large data transfers between Linux on A5 and MQX on M4, we have written a virtual filesystem based on the MCC library. It gives user a way to mount a Linux drive (or a part of it) into MQX, so you can use standard IO operations (fopen, fread, fwrite, ...) to handle the data. It is currently in experimental state. Should you (or anyone else) be interested in this functionality, please contact me.

[juangutierrez]

Hi Petr

Sounds very interesting. I would like to try it.

[karthigeyannata]

Thanks for your help.

Need another clarification. from A5 core , we will be writing the data and from M4 core , we will be reading the data.

If M4 core reads the structure while A5 core is writing the data in to it, then there is a possibility that the data read by M4 core may not be consistent.

Half of the data may be old and half of data may be new one.

Could you please help us how to overcome this issue?. Is there any hardware mutex available?.

When the hardware mutex is called , then the core itself stalled?

Please advise

[juangutierrez]

Yes there are 16 Hw Gates called Sema4. You can read more about it in RM Chapter 24 IPS_Semaphores

A snip of the code will look like this

/** SEMA4 - Register Layout Typedef */

typedef struct {

  __IO uint8_t Gate00;                            /**< Semaphores Gate 0 Register, offset: 0x0 */

  __IO uint8_t Gate01;                            /**< Semaphores Gate 1 Register, offset: 0x1 */

  __IO uint8_t Gate02;                            /**< Semaphores Gate 2 Register, offset: 0x2 */

  __IO uint8_t Gate03;                            /**< Semaphores Gate 3 Register, offset: 0x3 */

  __IO uint8_t Gate04;                            /**< Semaphores Gate 4 Register, offset: 0x4 */

  __IO uint8_t Gate05;                            /**< Semaphores Gate 5 Register, offset: 0x5 */

  __IO uint8_t Gate06;                            /**< Semaphores Gate 6 Register, offset: 0x6 */

  __IO uint8_t Gate07;                            /**< Semaphores Gate 7 Register, offset: 0x7 */

  __IO uint8_t Gate08;                            /**< Semaphores Gate 8 Register, offset: 0x8 */

  __IO uint8_t Gate09;                            /**< Semaphores Gate 9 Register, offset: 0x9 */

  __IO uint8_t Gate10;                            /**< Semaphores Gate 10 Register, offset: 0xA */

  __IO uint8_t Gate11;                            /**< Semaphores Gate 11 Register, offset: 0xB */

  __IO uint8_t Gate12;                            /**< Semaphores Gate 12 Register, offset: 0xC */

  __IO uint8_t Gate13;                            /**< Semaphores Gate 13 Register, offset: 0xD */

  __IO uint8_t Gate14;                            /**< Semaphores Gate 14 Register, offset: 0xE */

  __IO uint8_t Gate15;                            /**< Semaphores Gate 15 Register, offset: 0xF */

} SEMA4_Type;

/* SEMA4 - Peripheral instance base addresses */

#define SEMA4_BASE                              (0x4001D000u)

#define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)

#define UNLOCK      0x00

#define CORE0_LOCK  0x01

#define CORE1_LOCK  0x02

void hello_M4()

{

  /* Lock gate to write UART, then unlock */

  SEMA4->Gate01 = CORE1_LOCK;

  if(SEMA4->Gate01 == CORE1_LOCK)  {

      /* Output message from M4 */

      printf("Hello M4!\n");

  /* Unlock Semaphore */

  SEMA4->Gate01 = UNLOCK;

  }

}

Also is recommended used non cacheble section for the shared memory section to avoid coherency issues or make sure you are flushing the cache after writing

[karthigeyannata]

Thanks for your input.

Is it possible for core can wait for mutex till it is relieved by another core?

What happens to instruction execution while it is waiting for hardware mutex?

I hope, interrupt will keep running. What about the OS?

Thanks

karthi

[juangutierrez]

Is it possible for core can wait for mutex till it is relieved by another core?

   This should be implemented by software, usually the code should spin (checking in a while loop) for the gate to be unlocked by the other core. (The gate can only be unlocked by the locking processor)

  Optional interrupt notification after a failed lock write provides a mechanism to indicate when the gate is unlocked.

What happens to instruction execution while it is waiting for hardware mutex?

   The other processor do not stall, it continue executing code, it is responsibility of the user to spin/wait for the gate to be unlocked.

I hope, interrupt will keep running. What about the OS?

    yeah, they both keep running.

[anthony_huereca]

This is exactly what Multi-Core Communication (MCC) was created for. The two cores share memory space, which enables them to easily share data. MCC lets you share that data between a Linux-MQX or a MQX-MQX system easily. Documentation on it can be found at https://linuxlink.timesys.com/docs/wiki/engineering/userguide_vybrid_mcc and in the MQX installation folder at \doc\mcc

Note that if you share memory without using MCC and have cache enabled, make sure you are flushing the cache before the other core reads the data

[juangutierrez]

Yes, it is possible.

I guess the current ipc method relies on this, shared memory used to interchange messages.

I think this relies more on your compiler.

Some structures can have holes due to the alignment and this may vary depending on the compiler, but you can always packed your struct to alleviate a little bit this situation using a __attribute__((__packed__)) directive or some similar directive on your compiler.

Also, if possible align the member of your struct, to avoid the holes, like below.

struct s1 { //not aligned
   char a;
   int b; 
   char c;
   char d;
   char e;


}

struct s1 { //aligned
   int b;
   char a;
   char c;
   char d;
   char e;
}