Inter-core IRQ collisions on Vybrid

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Inter-core IRQ collisions on Vybrid

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kubiznak_petr
Contributor V

Having two GPIO inputs on the same PORT (say PTB23 and PTD10, both being on PORT2), how do I properly configure the interrupts, so that one GPIO triggers the ISR on A5 only and the second on M4 only?

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Carlos_Musich
NXP Employee
NXP Employee

Hi Petr,

sorry for delay. In this  case only main core is capable of manage interrupts.

Regards,

Carlos

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Carlos_Musich
NXP Employee
NXP Employee

Hi Petr,

sorry for delay. In this  case only main core is capable of manage interrupts.

Regards,

Carlos

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