Inter-core IRQ collisions on Vybrid

[kubiznak_petr]

Having two GPIO inputs on the same PORT (say PTB23 and PTD10, both being on PORT2), how do I properly configure the interrupts, so that one GPIO triggers the ISR on A5 only and the second on M4 only?

[Carlos_Musich · Accepted solution]

Hi Petr,

sorry for delay. In this  case only main core is capable of manage interrupts.

Regards,

Carlos