I2C2 Slave address

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I2C2 Slave address

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Contributor V

Dear community,

I am trying to interface Seiko-S35390A RTC to Vybrid with I2C2. when I set the destination address to 0x30 (0x60) and then write, I got IAAS flag of status register is set, and nothing is sent later.

I can both read and write 7 bytes to the register address 0x32(0x64).

So is the slave address of Vybrid I2C2 channel 0x60? If so, may I change it to any other value?

Best regards.

Mehmet Ali Ipin

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NXP Employee
NXP Employee

Have you tried by just checking I2Cx_IBSR.TCF to wait for the Transfer Completion?

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Senior Contributor V

Dear Mehmet Ali Ipin,

I am not a software person but will still try to help you, at least until our software guys return from their holiday vacations.

  • Please, take a look at the 'I2C memory map' table (specifically '400E_6000 / I2C Bus Address Register (I2C2_IBAD)') as well as the '48.4.3 I2C Bus Address Register (I2Cx_IBAD)' section ("This register contains the address the I2C Bus will respond to when addressed as a slave."). The default (out-of-reset) value is 0x00, and there are no value limitations mentioned here for this register.

        How are you using / configuring this specific register, please?

  • May you also refer me to all the registers in your problem description, please? - Including their addresses and the Reference Manual pages they are described on.

Sincerely, Naoum Gitnik.

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Contributor V

Dear Naoum,

I am using MQX. S35390A RTC I2C read is not suitable to work with MQX fwrite. Therefore I removed fwrite to write the address and  inserted the following codes, and now I ca read and write the registers of  S35390A.

But between the start condition and the data bits, there are about 10 miliseconds, even my I2C clock is 400 KHz.

If you know  the reason of this delay (with the below instructions) I would be grateful to you if you help.

Best regards.

Mehmet Ali Ipin.

   printf ("  I2C start, send address and get ack ... ");

   // fwrite (&param, 1, 0, fd);

   while( 1 == (I2C2_IBSR&QI2C_I2SR_IBB));

   I2C2_IBCR|=QI2C_I2CR_MDIS; // Disable I2C2 module.

   I2C2_IBCR|=QI2C_I2CR_MS; //  set Master mode

   I2C2_IBCR&=~QI2C_I2CR_TX; //  Set TX

   I2C2_IBCR&=~QI2C_I2CR_MDIS; //Enable I2C2 module; QI2C_I2CR_TX

   param = eRTCcommand*2+1;

   I2C2_IBDR = param;

   while( 0 == (I2C2_IBSR&QI2C_I2SR_IBB));

   /* Check ack (device exists) */

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Senior Contributor V

Dear Mehmet Ali Ipin,

Thanks for good news!

Before I involve a software person in this issue, may you clarify the below aspects, please?

  • Do you have a pull-up resistor on your I2C data line? If so, what value? - It is recommended to have 1.5K (for he highest speed possible in the spec, e.g. see Effects of Varying I2C Pull-Up Resistors). [The I2C clock line has a totem-pole output type hence no pull-up needed.]
  • While designing your code, have you used any of our examples? If so, is the 10-millisecond delay mentioned by you present in our code as well?

Sincerely, Naoum Gitnik.

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Contributor V

Dear Naoum,

Thanks for your helps,

  • I have 1K pull up resistors on both SDA and SCL lines. Both 400 Kbps and 100 Kbps clocks are working on I2C2 without a problem.
  • Yes I used the fwrite/fread functions of MQX. But the status reegister reading S35390A with fwrite is not suitable with MQX fwrite. S35390A requires status address writing with R/W bit is set to 1 and then read, but MQX fwrite generates the address with R/W bit is set to 0, therefore reading the register is not possible. There is no 10 milisecond delay when we use fwrite/fread, both reading a register of is not possible after fwrite.I developed my code according to the ref manual. May be a control bit should be set before start condition, or may be I should check another status register. If we use fwrite, start bit is similar to other bits period. I wish the start condition to be few miliseconds..

Best regards.

Mehmet Ali İpin

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NXP Employee
NXP Employee

Hi MehmetAliIpin

I think the problem might be that the destination address needs to be sent before the data.

The address should be shifted one bit to the left. Also I think is better to wait for the IBIF flag instead.

   I2C2_IBCR|=QI2C_I2CR_MS; //  set Master mode

   _PSP_SYNC();

   I2C2_IBCR&=~QI2C_I2CR_TX; //  Set TX

   _PSP_SYNC();

  I2C2_IBDR = (SLAVE_ADDR << 1) | I2C_OPERATION_WRITE;

  while( 0 == (I2C2_IBSR&QI2C_I2SR_IBIF)) {_PSP_SYNC();};   /* wait for address transferred */

   param = eRTCcommand*2+1;

   I2C2_IBDR = param;

   while( 0 == (I2C2_IBSR&QI2C_I2SR_IBB));

Would you try and let us know if it helps, please?

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Contributor V

Dear Juan

   I2C2_IBDR = (eRTCcommand << 1) | I2C_OPERATION_WRITE;

     Program is hanged on the line   // while( 0 == (I2C2_IBSR&QI2C_I2SR_IBIF)) {_PSP_SYNC();};   /* wait for address transferred */

   while( 0 == (I2C2_IBSR&QI2C_I2SR_IBB));

   {_PSP_SYNC();}

if I just check the I2SR_IBB, program continues, but takes to much time as I wrote before..

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NXP Employee
NXP Employee


Hi


From Section 48.4.7 I2Cx_IBDR of Vybrid RM:

In master transmit mode, the first byte of data written to IBDR following assertion of MSSL is used for the address transfer and should comprise the calling address (in position DATA[7:1]) concatenated with the required R/ W bit (in position D0).

That is why I suggested to add the next command

  I2C2_IBDR = (SLAVE_ADDR << 1) | I2C_OPERATION_WRITE;

  while( 0 == (I2C2_IBSR&QI2C_I2SR_IBIF)) {_PSP_SYNC();};  /* wait for address transferred */


where: I2C_OPERATION_WRITE = 0


However you stated that:

S35390A requires status address writing with R/W bit is set to 1 and then read, but MQX fwrite generates the address with R/W bit is set to 0, therefore reading the register is not possible


fwrite sets the IBDR register with the slave address with the R/W set to 0 (Just as I suggested above).

So, if you said you that S35390A expects a R/W = 1, the you should adjust the I2C_OPERATION_WRITE to be a 1 instead.


Also, this only applies for the FIRST data written to IBDR, next write I think does not need the R/W bit to be set

So, does the S35390A really needs the R/W to be set like below for the next IBDR write??

      I2C2_IBDR = (eRTCcommand << 1) | I2C_OPERATION_WRITE

or be just like

     I2C2_IBDR = eRTCcommand



Another option you can try is to modify directly the MQX code for the tx/rx functions called by fwrite/fread to make them suitable for the S35390A expectations.

You can find these functions at Freescale_MQX_4_0\mqx\source\io\i2c\polled\i2c_pol_qi2c.c.

Look for _qi2c_polled_rx (called by fread),

_qi2c_polled_tx (called by fwrite)

and _qi2c_polled_rx_tx functions (called by above functions)



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Contributor V

Dear Juan,

Thank you for your informations,

There are about 10 registers in S35390A, which might be accessed as different I2C addresses. So instead of one device address in I2C bus, there are about 10 addresses(registers like read status1, write status1, read status 2, write data register, read data register, ...). Any register can be read by adding one to its address, or can be written with only its read access address.

There is nothing wrong with the usage of R/W bit of I2C bus for S35390;  if R/W bit is one, then the addressed register is read next

if R/W bit is 0 then the next data on the bus is written to the register of S35390; So I eRTCcommand  is mainly the right shifted address of each register to be read/written.

I can both read and write the any register of S35390A, the only thing that I want to improve is, it takes 4-5 miliseconds to generate start bit with following command. while( 0 == (I2C2_IBSR&QI2C_I2SR_IBIF)) {_PSP_SYNC(); I wonder if there is another way to reduce this time to i.e 10-20 microseconds, by checking I2C register bit.

Thanks and with my best regards.

Mehmet Ali Ipin.

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NXP Employee
NXP Employee

Have you tried by just checking I2Cx_IBSR.TCF to wait for the Transfer Completion?

View solution in original post

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Senior Contributor V

Dear Mehmet Ali Ipin,

Let me ask you something a bit off-topic...

We do not get I2C support requests that frequently, which makes us think that our I2C interface's design is quite common.

At the same time, while monitoring this thread, I noticed a lot of S35390A component's details mentioned in it, which is making me think that perhaps this component might have its own peculiarities and it might be more efficient for you to clarify them with Seiko's Customer Support? Have you tried that? - Unlike us, they are supposed to know all its "fine aspects".

Sincerely, Naoum Gitnik.

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Senior Contributor V

juangutierrez, have you ever bumped into such a situation, please?

Thanks, Naoum Gitnik.

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NXP Apps Support
NXP Apps Support

juangutierrez any comment?

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Contributor V

Dear Naoum,

Thank you for your helps,

With monitoring the I2C2 status and control registers' bits, I noticed that when NOACK flag is set, the MQX fread and/or fwrite functions locked. I sollved the lock with these commands:

  I2C2_IBCR|=QI2C_I2CR_MDIS;// Disable I2C2 module.
  I2C2_IBCR|=QI2C_I2CR_MS;//  set Master mode
  I2C2_IBCR&=~QI2C_I2CR_NOAK;// clear NO ACK bit
  I2C2_IBSR = 0;
  I2C2_IBCR&=~QI2C_I2CR_MDIS; //Ensable I2C2 module; QI2C_I2CR_TX

I passed the lock, can read and write all registers, except one register, its address is 0x60. I will continue to test..

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