I2C timing settings and adjustment.

[takashitakahash]

There are does not fit in the receiver side microcomputer ratings results investigated a I2C waveform output timings.

Refer the Table 65 of I2C output timing specifications of VYBRIDRSERIESEC Rev7, 11 / 2014 , The P79 No6 No7 MAX values can be disclosed?

No6   Data setup time  spec is 2 PER_CLK Cycle=300nsec , but   receiver side microcomputer  spec is normalmode=250nsec and Highspeedmode=100nsec

No7 is Start condition setup time (for repeated start condition only) is 20 PER_CLK Cycle=0.3 μ sec, but   receiver side microcomputer  spec is normalmode=4.7 μ sec and Highspeedmode=0.6 μ sec.

And , Will also register settings can be adjusted the Data setup time  and Start condition setup time?  .

[VilemZ]

Hi Takashi,

Do you really need MAX values of timing? I think, that MAX values is not important for this.

And it seems, that values of No6 and No7 are rights. Or if you need change Data setup time, you can change PER_CLK by divider.

Best regards

Vilem

[takashitakahash]

Dear Vilem

Thank you for your replay.

I understand and refer the Vybrid RM Table48-51, dividing the PER_CLK.

Can be adjustment SCL,SDA,SCL.

But the No6 and No7 of VYBRIDRSERIESEC_Rev_7.pdf's "I think look at Table 65, cannot adjust clock cycles if the fixed.

This time Base Clock of I2C is 67. 4 MHz in the fixed use.

No6 Data set up time and No7 Start condition setup time can be adjusted?

[VilemZ · Accepted solution]

Hi Takashi,

In table 65 on VYBRIDRSERIESEC_Rev_7 are only minimum values. These values are depend on PER_CLK (Table 9-6 on VYBRID RM).

And then, you can modify values by prescaler (Table 48-51 on VYBRID RM).

Is it clear?

Best Regards,

Vilem

[takashitakahash]

Dear Vilem.

Thanks a lot ,I understand.

Thanks,

Best Regards.