I2C Clock Stretching in Vybrid

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I2C Clock Stretching in Vybrid

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srebbago
Contributor I

Hi ,

I want to know how to enable I2C clock stretching in Vybrid F-series. In reference manual(VYBRIDRM.pdf), I have found the below data(snap shot). But, didn't get information about which register/pin will set clock stretching. or Is clock stretching is enabled default in Vybrid?.

Give me clarification on this ASAP.

Thank you.pastedImage_0.png

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This an automatic process.

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jiri-b36968
NXP Employee
NXP Employee

Hello Siva,

clock stretching is a feature of I2C itself. It is always enabled. Any slave can slow down data transfer controlled by the master by holding CLK low for necessary time after the master sets CLK low. The master will continue with transfer once CLK is released.

/Jiri