Hello,
I want to connect FPGA and Vybrid with 32bit data bus and over 10bit address (acting like SRAM).
Vybrid series have 32-bit flexbus but must use multiplexing address and data.
If ddr3 slave interface can be implemented in FPGA and connect ddr3 interface of Vybrid, can it workable?
Hello,
only special pins (DDR_xxx, controlled by DDRMC) should be used for DDR3.
Hardly FPGA based approach (via FlexBus) can provide reliable solution.
Have a great day,
Yuri
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