I am trying to debug DDR3 issues on a new hardware design.

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I am trying to debug DDR3 issues on a new hardware design.

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mplseng
Contributor II

I am trying to debug DDR3 issues on a new hardware design. I would like to slow the DDR accesses to help distinguish between layout and timing issues. I had hoped I could change the ARM_CLK_DIV parameter in the CCM_CACCR register. However, if I change the value from the current setting (0) to anything else, any read/write access to DDR address space “hang”. Any ideas what I'm missing?

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mplseng
Contributor II

Subsequent to this post, I've learnt the minimum speed, at least for the DDR3 chip we are using is 300 MHz.

The idea of "slowing down" the interface is/was unworkable. Changing from a 396 MHz frequency to a 300 MHz was not the significant change I was looking for. Additionally, the FAE for Micron, clearly indicated the chip would work best when operated with a clock that approximates a JEDEC standard which in our case is 400 MHz (DDR3-800).

The original issue was a layout issue which we resolved. Thanks for the responses.

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mplseng
Contributor II

Subsequent to this post, I've learnt the minimum speed, at least for the DDR3 chip we are using is 300 MHz.

The idea of "slowing down" the interface is/was unworkable. Changing from a 396 MHz frequency to a 300 MHz was not the significant change I was looking for. Additionally, the FAE for Micron, clearly indicated the chip would work best when operated with a clock that approximates a JEDEC standard which in our case is 400 MHz (DDR3-800).

The original issue was a layout issue which we resolved. Thanks for the responses.

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naoumgitnik
Senior Contributor V

Hello Bob,

Have you used any Freescale design as a starting point for HW and/or SW, please?

Regards, Naoum Gitnik.

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mplseng
Contributor II

Yes on both counts.

During our testing, we used the original Timesys DDR configuration, the updated Timesys DDR configuration, and Freescale manufacturing tool uboot configuration.

We found a layout issue which was causing the original failure. Now we are moving on to the next issue.

The idea is slowing down the whole system would result in a more tolerant implementation of DDR3 and allow us to move forward on other hardware checkout while we are still working on the DDR issues.

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naoumgitnik
Senior Contributor V

Dear Bob,

  • You mentioned the layout issue - was it caused by our design you copied?
  • Are you trying to lower the DDR clock frequency? E.g., to its minimum of 100MHz?

Regards, Naoum Gitnik / Freescale AE.

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