How should unused Vybrid DDR pins be connected?

[richarddonkin]

I am using the VF5xx in a design for which the 1.5MB on-chip RAM is sufficient.

How should the DDR pins be connected in the design, given that they are unused?

So far I am assuming the following.

1. SDRAMC_VDD2P5 pins are connected to DECAP_V25_LDO_OUT.

2. SDRAMC_VDD1P5 pins are left floating

3. The following pins are connected to VSS:

    DDR_A, DDR_D, DDR_BA, DDR_DQM, DDR_DQS, DDR_ODT, DDR_CAS,

    DDR_CKE, DDR_CLK, DDR_CS, DDR_RAS, DDR_WE,

    DDR_VREF, DDR_ZQ, DDR_RESET.

Is this correct?

Richard

[naoumgitnik · Accepted solution]

Hello Richard,

1. Correct.
2. Correct (based on the "Power Sequencing" table in the Datasheet - the SDRAMC_VDD1P5 supply can come in any order).
3. With the DDR controller having no power, you may leave them floating. In case you insist on pulling these IOs down, they have configurable built-in pull-ups/downs - see "section "5.3 Functional Description" of "Vybrid Reference Manual, Rev. 5, 07/2013" for details. I prefer to not connect IOs directly to GND in principle - what if, due to a SW bug, it gets configured as an output and due to that overloaded and possibly damaged?

Sincerely, Naoum Gitnik.

[ChrisNielsen]

A) Rev 5 DS Figure 4 shows LDO2P5 supplying not just DDR but also several internal PLLs.  Based on those extra connections, should the Tower capacitors on DECAP_V25_LDO_OUT be retained? (10u, 3x0.1u, 3x470p)  Some LDOs are unstable without a certain minimum bulk capacitance on the output.  It also seems like some decoupling (0.1u, 470p) might be helpful for keeping the noise level low for the sensitive PLL circuits?

B) Floating inputs make me nervous in general.  Might it be better if we ground it?  Do you see higher risk in grounding it as opposed to floating?  I do see the note on page 31 regarding floating the supply but it doesn't state which (1P5, 2P5) it is referring to.

Thanks, Chris