Hi community.
Our customer have video ADC clock frequency question.
Would you please Answer tomorrow 23 Oct, by 2015.
How many MHz speed of proc_clk input frequency of video AFE blocks .?
Refer from 9.10.13 Video ADC clock.
At frequencies below the formula is correct?
From 9.6.1.1 Typical PLL Configuration
PLL6(video PLL) PLL output=24M*44.33=1064MHz(This is PLL6main clock)
CCM_CSCDR1=1064/4=532MHz
Video ADC clock=532/4=133MHz
video ADC clock divide by 2 clock=66.5MHz
From Chapter 61 61.1 Introduction of Figure 61-1. Video subsystem block diagram
data clk= 66.5MHz
Solved! Go to Solution.
Hi, takashitakahashi
sorry for the late response as I need to confirm some information.
yes, your formula is right. just reminder, please configure CCM_CSCMR1 correctly.
9–8
VADC_CLK_SEL
Video ADC clock select
00 Divided PLL6 main clock, defined by CCM_CACRR[PLL6_CLK_DIV]
01 Divided PLL3 main clock, defined by CCM_CACRR[PLL3_CLK_DIV]
10 PLL3 main clock
11 Reserved
Hi, takashitakahashi
sorry for the late response as I need to confirm some information.
yes, your formula is right. just reminder, please configure CCM_CSCMR1 correctly.
9–8
VADC_CLK_SEL
Video ADC clock select
00 Divided PLL6 main clock, defined by CCM_CACRR[PLL6_CLK_DIV]
01 Divided PLL3 main clock, defined by CCM_CACRR[PLL3_CLK_DIV]
10 PLL3 main clock
11 Reserved