Help understanding resets: JTAG reset and debugging on VF61x

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Help understanding resets: JTAG reset and debugging on VF61x

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Senior Contributor I

Here I'm again, struggling to understand from the Vybrid documentation how does JTAG reset work, and how one is able to restart debugging just on one core (M4 in my case, but similarly on A5).

Can anyone explain how this works? How am I able to restart my debug session on the M4 core while leaving A5 running?  This is the case with the external HW debugger connected to the JTAG iface to the SoM.

It took me some time and some trial tests to understand that, any WDOG - A5, M4, CA5 - will reset the entire system, not just the relevant core.

And that it seems ( I still kinda cannot believe it!) you cannot restart the M4 core once you started it after the boot on the A5   [in my ignorant opinion, why would you make such a thing?]

I dunno how else to read it, but any reset that goes to SRC - Destructive, or Functional - seems to eventually reset the system and both cores.  (WDOGs are Functional,  so is JTAG reset)

But this can't apply for when the system is being debugged, right? So how / what resets just the core you working with leaving the other running on.

May be this question is really stupid, but spare a moment 

Please help !

Ok, I did find Chapter 9.11 System Debug.  So the 'magic' I'm looking must be from SJC,JTAGC.  ..

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Senior Contributor I

Ok, chapter 9/System Debug is a heavy read, if you never seen this stuff before..

But basically seems, through the systems JTAGC/SJC, external hw debugger is able to issue CM4 debug request, which puts the core into debug state and halts it. It then can also issue CM4 debug restart.  

Which probably then able to restart/reset the core execution from beginning without affecting the rest of the system?

Is this it then, no SRC involved, nothing to do with the system resets?