Debugging BSCAN test for Vybrid. Chip doesn't seem to respond correctly with this BSDL file

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Debugging BSCAN test for Vybrid. Chip doesn't seem to respond correctly with this BSDL file

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Contributor I

Hello,

I made a boundaryscan project for our Vybrid module with the "Cascon" tools from Göpel electronic.

The "infrastructure" test, which reads the Vybrid ID and checks the JTAG scanchain works fine.

But every other test I try fails, because none of the Vybrid pins seems to be driveable. The BSDL file contains no compliance pattern which means that there are no conditions which have to met to enable boundaryscan. The Vybrid CPU has two "test" pins (#T3 and #T1). Maybe I have to use these pins in some way (they are tied to GND)? There is no information about that in the datasheets.

Here are some information about the environment I use:

- Cascon 4.6.2b

- BSDL File VYBRID_364_F.bsdl Version 5

- Vybrid CPU marking "PVF65GS10CMK40 TEST REV B1" ( also tried step C3 )

Any help to get the boundaryscan test running is welcome :-)

Regards

Eric


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NXP Employee
NXP Employee

Eric,

Can you try the attached file.

Thanks

Ross

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NXP Employee
NXP Employee

Eric,

Can you try the attached file.

Thanks

Ross

View solution in original post

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NXP Employee
NXP Employee

Hi Eric,

I checked with the design team, there are no special requirements to enable BSDL, expectation is the supplied BSDL file should work. Can you create or generate a log file with perhaps some more detail on the sequence of events you are seeing, this may help us debug what is happening?

Thanks

Ross

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Contributor I

Hi  Ross,

I wrote two small CasLan based example programs (CasLan is the programming language of Cascon, Göpels boundaryscan tool).

I hope that I could explain the problem with these examples :-)

The hardware I use connects a CION chip U5_TH027 (this is a ASIC developed by Göpel which has good boundaryscan capabilities) to the Vybrid CPU U4_PCM052.

The picture shows the net based on the schematic netlist.

U5_TH027 Pin "PORT_C7"    ------ connector -------- connector ---------- U4_PCM052 Pin "PTB18"

Measuring the net with my Oscilloscope I could see that example 1 drives the net HIGH successfully.

Executing example two leads to no changes on the scope, but it also should drive the net HIGH. This is the problem I am talking about.

There is one wired additional information: executing the last DRSHIFT in example two causes the Vybrid RESETb pin to drive a LOW.

The scanchain is still working so it might not be a problem.

(There is a short "init sequence" not shown here which brings all ICs into sample mode and configures the used scan router.)

Example 1: drive the Cion Pin

    ENABLE (U5_TH027:PORT_C7);

    DH (U5_TH027:PORT_C7);

    DRSHIFT;

    ldi U5_TH027, EXTEST;

    IRSHIFT;

    DRSHIFT;   

   

Example two: drive the Vybrid Pin.

    ENABLE (U4_PCM052:PTB18);

    DH (U4_PCM052:PTB18);

    DRSHIFT;

    ldi U4_PCM052, EXTEST;

    IRSHIFT;

    DRSHIFT;    <-- Vybrid RESETB goes low   

Regards Eric

Vybrit_PTB18.jpg

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NXP Apps Support
NXP Apps Support

RossMcLuckie can you   continue with the  follow up on this case?

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