Hi
In Reference Manual there is a mismatch in section 26.6.1 Watchdog Control Register (WDOG_WCR) between the table and the graphic for WCR register
Dismiss the graphic. Table provides the correct information.
Besides that, I think your code is fine for a timeout around 32s
However take into consideration that the power-down counter is not affected by debug mode entry/exit.
For example, check next code
void wdbg_test()
{
reset_occurred = 0;
interrupt_handlers[128]= INTR_ROUTINE; // reset_occurred will be set inside this routine
SRC.SICR.B.WDOG_RST = 0x01; //Configure WDOGA5 reset as interrupt
// Starting WDOG debug mode test case
WDOGA5.WCR.R = 0x2736; //timeout 20s
printf("Start watchdog");
WDOGA5.WCR.B.WDE = 1;
printf("Wait here in debug mode for 20s... reset should not come");
//To continue: Manually disable the WDBG here
while(reset_occurred != 1); //Wait here for interrupt
}