Creating full isolation between the cores

[ippisl]

Hi,

Regarding vf6xx(cortex-a5/cortex-m4 cpu):

I want to create full isolation between 2 cores: one core will do communications , the other all the rest of the stuff including io.

I want the core that does communication have it's own memory and peripherals, But can't access in anyway the memory and peripherals of the other core. The only interface would be through the shared memory.

Is it possible to achieve this ? How ?

Thanks.

[timesyssupport · Accepted solution]

Hello,

You can use MCC, which uses shared SRAM, for communication between the two cores. For more information about MCC, you can see the user guide here:

Vybrid MCC User Guide For MCC Version 1.0 | Timesys Embedded Linux

However, peripheral isolation is currently not graceful between M4 and A5 - peripherals used in M4 and A5 are hardcoded in the Linux kernel and MQX source code. For complete isolation, you will need to customize the Linux kernel / mqx configuration and sources to achieve this.

Thanks, and let me know if you have any questions.

Timesys Support

[karina_valencia]

timesyssupport can you  help on this case?