Chip doesn't seem to work correctly with this BSDL files "Vybrid F Series 364MAPBGA BSDL Silicon Revision 1.1 (REV 0) " or "bga_364_v2.bsdl"

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Chip doesn't seem to work correctly with this BSDL files "Vybrid F Series 364MAPBGA BSDL Silicon Revision 1.1 (REV 0) " or "bga_364_v2.bsdl"

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Contributor II

Hi,

it seems that I have the same problem like " Debugging BSCAN test for Vybrid. Chip doesn't seem to respond correctly with this BSDL file  " resp. "Vybrid VF60 no output in JTAG boundary scan" .

Is there a newer BSDL file?

Best Regards,

Andreas

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Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

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Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

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NXP Apps Support
NXP Apps Support

richard_stulens​ now this is question :smileyhappy:

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NXP Employee
NXP Employee

Thanks Karina.

Andreaas,

The attached PDF describes the workaround for the issue.

Best regards,

Richard

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Contributor II

Hi Richard,

Thanks for workaround. I try it, in the next few days.

I give you feedback when I'm done.

Best Regards,

Andreas

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Contributor II

richard_stulens​ FYI

Hi Richard,

the company Göpel electronic has checked the workaround.

A FLASH test unfortunately I can't implement in this way.

The only opportunity that I here have, is the creation of a manual test.

Best Regards,

Andreas

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NXP Employee
NXP Employee

Hi Andreas,

If that cannot be implemented, you can try other methods like Manufacturing Tool. This uses the boot loader and USB interface to program external devices. More information can be found here.

Note: Manufacturing tool works only on parts that boot from the A5 core.

Best regards,

Richard

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Contributor II

Hi Richard,

in the thread  "Vybrid VF60 no output in JTAG boundary scan" you have written that "Design is still working on this issue to see if there is a better solution but for now there is no update.".

Do you have any new Information (update) to this issue?

Is a new BSDL-File available soon?

Best Regards,

Andreas

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NXP Employee
NXP Employee

Hi Andreas,

Thanks for pointing out that the final resolution was not added to the other thread. I have no added thid.

That thread is 2 years old by now and design came up with a workaround.

The document that I attached here earlier contains the update. The ultimate solution is to use the JTAG header, as per method 2 to precondition the output buffers. Only the second method will allow for programming external devices over JTAG.

Best regards,

Richard

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NXP Employee
NXP Employee

Andreas,

The issue with the JTAG programming is not the BSDL file and cannot be solved with a new BSDL file.

I have a document that describes how work around the issue bu I cannot add it to this thread.

Please create a new request as "New Question" (not as document). I cannot attach files to documents.

regards,

Richard

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