Cannot debug connect to M4 after watchdog reset

[dry]

Hello,
While debugging the M4 side, if the M4 watchdog reset happens and system restarts, I cannot connect to it with JLink unless I power cycle the board. Just reset does not help, have to power on / off the board.

Is this expected behavior?

[Yuri]

Hello

  From section 4.1.3 (Enabling a second core) of app note AN4947 (Understanding
Vybrid Architecture) :

“The second core is not clocked after reset. The special purpose register in system reset
controllers can hold an entry point for secondary core and an argument for entry function.
Once set, the clock for a secondary core can be enabled. From that moment, both cores
will run their own code.”

http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf  

Have a great day,
Yuri

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[dry]

Let me explain more the problem in my original question, in case there is misunderstanding.

I start with A5 booted, CM4 is not clocked and not enabled yet. Using JLink, I can connect to the CM4, upload and debug the firmware. Using JLink I can also restart that CM4 debugging session, without impacting on A5.

Next the WDOG-M4 is triggered and the system is reset (reset cause WDOG-M4), A5 boots and again CM4 is not enabled yet. Now with JLink i cannot connect to the target at all, to reset the core or upload the firmware. Even if I trigger external reset, I still cannot connect to it. Only if I power on , off the board (reset cause POR), (and again, A5 running but CM4 is still no enabled yet before JLink connects), then I can start debugging with JLink again on the M4.

This behavior looks like only affects JLink's ability to connect the CM4 and start it. I can, with software running on the A5, load the M4 firmware and enable CM4 and run it, after any of the watchdogs resets.

[Yuri]

Hello,

  Perhaps, it makes sense to consult with Jlink support ?

Regards,

Yuri.

[dry]

Hi Yuri,

I'm still missing something here.

The second core is also in reset after the SoC was power cycled (off, on), and so by this logic you highlighted above, I wouldn't be able to connect to it (as I wrote above with JLink)  in this case as well. But this is not what happening, as I can connect and debug it with JLink just fine after power cycling the board.

Also JLink probably has it's own means to reset the CM4 core, no? Else I would have to power cycle the board each time I want to reload/restart debugging firmware.

[dry]

Correction there:  "The second core is also not _clocked_ after the SoC was power cycled"....

[Yuri]

Hello,

   It is necessary to run the CM4 after reset, as described in section 

7.5.11 (Running Secondary Core) of VFxxx Controller Reference Manual.

http://www.nxp.com/assets/documents/data/en/reference-manuals/VFXXXRM.pdf 

Regards,

Yuri.

[dry]

Are you saying it is necessary for the CM4 to be running  before you can connect to it with JLink and debug on CM4?

[Yuri]

Yes,  it is necessary for the CM4 to be running  before you can connect to it with JLink and debug on CM4.

~Yuri.