Can QSPI1 & QSPI0 be active at the same time?

[taliazmanov]

Hi,

I'm currently working on an application that runs on a Vybrid MPU.

The application uses QSPI0 for the NOR FLASH access, and QSPI for a serial SRAM (NO1S830HA) access.

Both interfaces have to be active at the same time,

and as far as I've seen in your demo examples (configurations : svf522revb_m4, svf522revb_a5,twrvf65gs10_a5 and twrvf65gs10_m4) this option is disabled by software.

Since we are currently experiencing problems in the testing, I would have like to know whether this mode of operation is possible,

and if so - under which circumstances and what needs to be done in order to ensure its proper functioning.

     Thanks in advance,

             Tali

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[timesyssupport]

Hello Tali,

Are you developing for Linux, or MQX?

Thank you,

Timesys Support

[taliazmanov]

Hi,

I’m developing for MQX 4.0.2.

Thanks,

Tali

[timesyssupport]

Which version of the Vybrid processor are you developing for? VF6, or VF5? Is this evaluation hardware, or a custom design?

Thank you,

Timesys Support

[taliazmanov]

Hi,

The Vybrid version is vF5, and this is a custom design board.

Regards,

Tali.

[alejandrolozan1]

Hi Tail,

Can you describe the behavior you are facing? As I see, there should not be any issue when using both  QSPI modules. They are mapped to different memory locations.

Best Regards,

Alejandro

[taliazmanov]

Hi Alejandro,

The behaviour I’m seeing is different performance results in read operations when working in a standalone single-core configuration,

Where the driver is a single task running on M4 only, and is based on your svf522revb_m4 example that comes with the Vybrid MQX 4.1 s/w,

With only QSPI1 enabled and active,

Where the results for reading a 64 bytes block were fixed on 47 microseconds,

And our application configuration, which is a dual core (with A5 active also) where the QSPI1 driver is implemented as the highest priority pre-emptive task,

And the QSPI0 is used for the NOR-FLASH (where the code is located) which is being accessed by A5.

In the application configuration (dual core, dual QSPI i/f’s) I’ve got inconsistent results for the read operation in the range of 360-590 microsec.,

Which suggest that the read operation, although implemented as a highest priority pre-emptive task, was interrupted by another event/s.

I’ve checked in the QSPI example drivers that come with the Vybrid MQX 4.1 s/w, and saw that in all of them,

The option of both i/f’s (QSPI0 & QSPI1) active at the same time is disabled by s/w ( please see BSP_QUADSPI_MEMORY_CHANNEL flag),

And wondered whether that could be the reason.

Looking forward to your answer,

Thanks,

Tali

[alejandrolozan1]

Hi Tali,

I have checked the latest MQX realease 4.2 and I have not found the BSP_QUADSPI_MEMORY_CHANNEL flag/macro.

Have you tried the newest version?

/Alejandro

[karina_valencia]

taliazmanov​ did you get previous update?

[taliazmanov]

Hi, not sure what you mean by previous update

[karina_valencia]

I mean the  comment  from Alejandro.

[karina_valencia]

alejandrolozano​ do you have an update?

[karina_valencia]

timesyssupport​ can you help to review this case?