Are ISD2FA, ISD3FA, ISD2FB and ISD3FB implemented in the QSPI peripheral?

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Are ISD2FA, ISD3FA, ISD2FB and ISD3FB implemented in the QSPI peripheral?

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beat
Contributor II

I see the flags ISD2FA, ISD3FA, ISD2FB and ISD3FB mentioned in VYBRIDRM v5, but the fields are not documented in the MCR register details.  These are also mentioned in app note AN4512.  Is this feature actually implemented in the Vybrid QSPI peripheral, or does the software need to change those pins to GPIO to control them?

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naoumgitnik
Senior Contributor V

Dear Russ,

Before we proceed further, have you looked at the Re: QSPI I/03 Diven Low during all Single bit accesses thread also discussing these flags?

Regards, Naoum Gitnik.

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naoumgitnik
Senior Contributor V

Dear Russ,

Before we proceed further, have you looked at the Re: QSPI I/03 Diven Low during all Single bit accesses thread also discussing these flags?

Regards, Naoum Gitnik.

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beat
Contributor II

Ah, yes.  It looks like the search doesn't include the content of posts...

EDIT: I learned the difference between the "Search" and "Filter" dialogs.  The "Filter" field was not searching thoroughly.

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