About setting PHY Register 03 and PHY Register 04 part2

cancel
Showing results for 
Search instead for 
Did you mean: 

About setting PHY Register 03 and PHY Register 04 part2

Jump to solution
210 Views
keisukewatanabe
Contributor III

Dear support,

34.5.166 PHY Register 03 (DDRMC_PHY03)

34.5.167 PHY Register 04 (DDRMC_PHY04)

I do not know DDR3 SDRAM to be used is determined whether this register value in any timing.

Please tell me by a name defined in JEDEC.

Best regards,

Keisuke Watanabe

Labels (1)
0 Kudos
1 Solution
45 Views
ioseph_martinez
NXP Employee
NXP Employee

Hello keisukewatanabe

As for phy03, this is an internal parameter for the DLL inside the phy controller. It does not correspond to any JEDEC parameter. I have done some tests where I automatically test all the different values for the stat point to find out which work best, my results indicate that DDR_PHY003 = 0x00000020 other values near that may work but I recommend you to use that one.

For phy04, I could not find a direct relationship between from a JEDEC timing because I understand that DQS is expected to be 90 degrees aligned to the DQ signals. So this parameters helps to fine tune this alignment. The recommendation is using a value of 0x20 as in:  DDR_PHY004 = 0x00002000 although other values may work, as soon as you start deviating far from this centered value it may fail. More details already found at https://community.freescale.com/thread/311918

best regards,

Ioseph

View solution in original post

0 Kudos
1 Reply
46 Views
ioseph_martinez
NXP Employee
NXP Employee

Hello keisukewatanabe

As for phy03, this is an internal parameter for the DLL inside the phy controller. It does not correspond to any JEDEC parameter. I have done some tests where I automatically test all the different values for the stat point to find out which work best, my results indicate that DDR_PHY003 = 0x00000020 other values near that may work but I recommend you to use that one.

For phy04, I could not find a direct relationship between from a JEDEC timing because I understand that DQS is expected to be 90 degrees aligned to the DQ signals. So this parameters helps to fine tune this alignment. The recommendation is using a value of 0x20 as in:  DDR_PHY004 = 0x00002000 although other values may work, as soon as you start deviating far from this centered value it may fail. More details already found at https://community.freescale.com/thread/311918

best regards,

Ioseph

View solution in original post

0 Kudos