About Watch Dog Timer in STOP and DOZE mode

[norihiromichiga]

Hello NXP team,

I'm modifying my original comment I posted in other day.

I need NXP's support asap to solve our problem. Please advise me how to stop WDT when Vybrid is in STOP mode.

According to "VYBRIDRM: Vybrid Reference Manual: F Series - Reference Manual (REV 8)", page 1248 , I think I can stop WDT operation when Vybrid is in STOP mode. But in fact, I can't stop WDT in STOP mode and WDT keeps working even I set WDOG_WCR to "0x3F33" before I put Vybrid to STOP mode.  Could you advise me if any additional settings are needed to stop WDT in STOP mode?  Or this behavior is not supported in Vybrid?

===============

　9.7.5.4.1 STOP and DOZE mode

　　If the WDOG timer disable bit for low power STOP and DOZE mode (WDZST) bit in

　　the Watchdog Control Register (WDOG_WCR), is cleared, the WDOG timer continues

　　to operate using the low frequency reference clock. If the low power enable (WDZST) bit

　　is set, the WDOG timer operation will be suspended in low power STOP or DOZE mode.

　　Upon exiting low power STOP or DOZE mode, the WDOG operation returns to what it

　　was prior to entering the STOP or DOZE mode.

===============

Thanks,

Norihiro Michigami
AVNET

[norihiromichiga]

Hello folks,

Thank you for your comment.

I understood that NXP also observed the same result (WDOG timer still runs you tried to stop in STOP mode) as our customer.

I think your SOC team will verify if this feature is available on Vybrid device.

If just some register settings are missing to use this feature, please let us know additional register settings.

If this feature is not correctly implemented on Vybrid hardware, please let us know if there is any alternative way to avoid WDOG reset during STOP mode.

This is high priority issue at our customer, so you quick replay is very appreciated.

Thanks,

Norihiro Michigami

AVNET

[alfred_liu]

Hi，b47504​

from our RM description, this may be a issue related to SOC.

please create a CT to invlove SOC RD team look at it together.

Hi, karinavalencia​

we need involve SOC team of Vybrid in this issue, Is a general CT OK for Vybrid support?

thanks

[karina_valencia]

HI Alfred,  CTs  are  created in the same project used  for i.MX.

jiri-b36968​ can you  comment if is better to proceed in other   form?

[b47504]

Alfred1z​,  I can reproduce the issue as the customer said,  so what's the next step?

[soichiyamamoto]

Hellio,

I think that I can inspect it by a project of ”\Vybrid Sample Code\vybrid_sc\build\ds5\projects\low_power” of the following sample.

Sample Code for Vybrid Controller Tower System

Best regards,

soichi

[norihiromichiga]

Hello Yuan-san,

In fact, this problem was reported by our customer who used Vybrid.

So, sorry, it is difficult to get such source code from our customer.

I believe NXP has a sample code which demonstrate how to pus Vybrid into STOP mode.

Is it possible to add source code which stops WDT timer?

Or if your fact has a code which was used to verify WDT timer in STOP mode,

please provide it us.

Thanks,

Norihiro Michigami

AVNET

[b47504]

No, I have no the code which work directly for this case in hand . It would take the time to ceate the specific code and test envrionment.

[norihiromichiga]

Hello Weisong-san,

Thank you for your update.  Did you already try the similar test on your board?

Sorry for pushing you, but we need your reply asap.

Thanks,

Norihiro Michigami
AVNET

[b47504]

Can you share your test code to us? Then it can help us to set up the test environment in a short time. Thanks.

[alfred_liu]

Hi, Norihiro Michigami

I am setting up the board here and will try on the board.

will update you the result soon.

[norihiromichiga]

Hello Weisong-san,

Here is register values we read out from Vybrid _just_ before we put Vybrid in CPU sleep mode.

We tried 6 cases to see if we can avoid watch dog timer reset while CPU was in sleep mode.

In all cases, watch dog timer reset happens.

(a) We set WDW + WDZST + WDBG to Suspend. Register value is 0x3FB7

(b) We set WDW + WDBG to Suspend. Register value is 0x3FB6

(c) We set WDZST + WDBG to Suspend.  Register value is 0x3F37

(d) We set WDW + WDZST to Suspend.  Register value is 0x3FB5

(e) We set WDW to Suspend. Register value is 0x3FB4

(f)  We set WDZST to Suspend. Register value is 0x3F35

Thanks,

Norihiro Michigami
AVNET

[alfred_liu]

Hi, Norihiro Michigami

could you read out the value of WDOG_WCR before you go into STOP mode?

I want to make sure you have written it successfully because many bits in this register are "write-once".

[norihiromichiga]

Hello folks,

Thank you for your work on my question.

I believe it is not so complicated question which is directly related to hardware (not software issue).

So, if possible, could you quickly check if this feature ( WDOG can be suspended by WDOG_WCR) works on your reference board as RM said?  If you could see the same result as us, we need to look into another way to stop WDOG.

In fact, this question comes from our important customer and we need to a way to stop WDOG timer in STOP mode asap.

Your understanding will be very appreciated.

Norihiro Michigami

AVNET

[karina_valencia]

rendy​ can you help to review this case and share your comments?

[norihiromichiga]

Hello NXP team,

Please let me add one more comment about our experiment on WDOG timer.

Regardless of setting of WDBG bit (0 or 1), WDOG timer still runs in STOP MODE and WDOG RESET happens after expiration of WDOG Timer.

Thanks,

Norihiro Michigami

AVNET

[alfred_liu]

Hi, karinavalencia​

Basically it's a software question. (software setting in code).

please assign it to software SE for checking.

thanks