34.5.165 PHY Register 02 (DDRMC_PHY02) 29-25bit

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34.5.165 PHY Register 02 (DDRMC_PHY02) 29-25bit

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keisukewatanabe
Contributor III

Dear support,

29 EN_HALF_CAS

27 SW_HALF_CYCLE_SHIFT

25 WRLVL_CLKDL

Please tell me the timing chart set by these.

Best regards,

Keisuke Watanabe

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ioseph_martinez
NXP Employee
NXP Employee

Hi keisukewatanabe

Sorry, we don't have time diagrams for this signals but I can provide some more data on this signals and how/when to configure.

Regarding EN_HALF_CAS:

This parameter works together with Gate_cfg (see this) it modifies the same internal signal in the phy controller. Similarly, typically will be set to zero and adjusted when there are read fails (probably related to PCB delays)

Regarding SW_HALF_CYCLE_SHIFT:

The DQS signal is generated based on the CLK reference internally. This parameter tells if DQS should be delayed half cycle or not. Typically there is no need to adjust this parameter since the data is already adjusted respect to DQS properly with the DLL_WRITE_DL in PHY04

Regarding SW_HALF_CYCLE_SHIFT:

The DQS signal is generated based on the CLK reference internally. This parameter tells if DQS should be delayed half cycle or not. Typically there is no need to adjust this parameter since the data is already adjusted respect to DQS properly with the DLL_WRITE_DL in PHY04

Best Regards,

Ioseph

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ioseph_martinez
NXP Employee
NXP Employee

Hi keisukewatanabe

Sorry, we don't have time diagrams for this signals but I can provide some more data on this signals and how/when to configure.

Regarding EN_HALF_CAS:

This parameter works together with Gate_cfg (see this) it modifies the same internal signal in the phy controller. Similarly, typically will be set to zero and adjusted when there are read fails (probably related to PCB delays)

Regarding SW_HALF_CYCLE_SHIFT:

The DQS signal is generated based on the CLK reference internally. This parameter tells if DQS should be delayed half cycle or not. Typically there is no need to adjust this parameter since the data is already adjusted respect to DQS properly with the DLL_WRITE_DL in PHY04

Regarding SW_HALF_CYCLE_SHIFT:

The DQS signal is generated based on the CLK reference internally. This parameter tells if DQS should be delayed half cycle or not. Typically there is no need to adjust this parameter since the data is already adjusted respect to DQS properly with the DLL_WRITE_DL in PHY04

Best Regards,

Ioseph

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