34.5.165 PHY Register 02 (DDRMC_PHY02) 2–0 Gate_CFG

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34.5.165 PHY Register 02 (DDRMC_PHY02) 2–0 Gate_CFG

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keisukewatanabe
Contributor III

Dear support,

The 2-0 Gate_CFG is an area used at the time of leveling, it is not necessary to set a specific value?

Best regards,

Keisuke Watanabe

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ioseph_martinez
NXP Employee
NXP Employee

Hi keisukewatanabe

Please note that this register controls an internal signal, inside the phy controller which opens the gate to receive the DQS signal. Is not only used during time leveling.

Typically you would configure this value as zero. (DDR_PHY002 = 0x00200000) but there may be cases that due PCB design that some adjustment is required. (when there is read failures)

Best Regards,

Ioseph

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ioseph_martinez
NXP Employee
NXP Employee

Hi keisukewatanabe

Please note that this register controls an internal signal, inside the phy controller which opens the gate to receive the DQS signal. Is not only used during time leveling.

Typically you would configure this value as zero. (DDR_PHY002 = 0x00200000) but there may be cases that due PCB design that some adjustment is required. (when there is read failures)

Best Regards,

Ioseph

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