34.5.163 PHY Register 00 (DDRMC_PHY00)

[keisukewatanabe]

Dear support,

I want to know the "enable time" and "disable time" that written the RM 34.5.163 PHY Register 00 (DDRMC_PHY00).

Please send the material in the timing diagram.

In addition, please tell me of "the starting point of the DQS pad output enable window","the ending point of the DQS pad output enable window", the correspondence between timing defined by JEDEC (JESD79).

Best regards,

Keisuke Watanabe

[ioseph_martinez · Accepted solution]

Hello,

I hope I can help a bit on this questions from what I understand from the manual.

The memory controller has many registers to fine tune the operation of the controller but most of the cases the best choice is go and use the recommended values.

In the case of TSEL_START and END there is not timing diagram available. But I can provide further explanation: What it controls what value will be used as termination based on PHY_52 register.(DQ status while read and off operation) In this case, the recommended value is having both start and end configured to the same value = 0x2. So the delta is zero and termination is not switched from value. I recommend having it set to 0x2.

In the case of OE_START and END is different. (take a look on 34.6.15.10) Controls the timing of the output enable which is internal to the controller which controls when DQ signal will be active output. It will not be on the JEDEC standard. You have the option to tune this value but recommendation is used the recommended values.

Best Regards,

Ioseph