Overview of the I3C Interface, Successor of the Well-Known I2C Interface

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Overview of the I3C Interface, Successor of the Well-Known I2C Interface

Overview of the I3C Interface, Successor of the Well-Known I2C Interface

Learn how to solve your I2C system challenges by deploying I3C. Our experts will provide a comprehensive introduction into the new MIPI I3C interface and its advantages compared to the well-known, I2C interface. This session gives an overview of how to develop I3C-based systems as well as provide a view of NXP’s MIPI I3C slave RTL, which is the first verified, freely available RTL source code available for download.

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I downloaded the RTL and Free License from "Free MIPI I3C Slave IP for both MIPI member and non-member companies" site. The tests in this package use "tst_i3c_master_model.v". I don't see this file in the package I downloaded. Is it not part of the free license?

Hi Nutan - The content owner for the material answered with the following information.

the I3C master is not part of the free IP. Only the slave is.
The master IP is available e.g. through Silvaco.

I hope this helps.

Thanks!

Hi Renee,

Thank you for your reply.

I understand that the I3C Master is not part of the free IP package. The file “tst_i3c_master_model.v” I mentioned is not the I2C Master RTL. It is a model used in the Slave IP’s test files in the auton_display directory, and is necessary for simulating the tests. If we cannot simulate the free Slave IP, it is of no use.

All the test files under auton_display directory have the following line:

`include "tst_i3c_master_model.v"

This is an I3C master model, not the RTL.

Thank you,

Nutan

Hi Nutan -

I received the following from the content owners. Thanks.

Sorry, to agree with you: the free slave RTL is slave only and does not provide full test. I will eventually add a vectored test for it for both Autonomous and APB. The Master is not included.

 

 I understand that the I3C Master is not part of the free IP package. The file “tst_i3c_master_model.v” I mentioned is not the I2C Master RTL. It is a model used in the Slave IP’s test files in the auton_display directory, and is necessary for simulating the tests. If we cannot simulate the free Slave IP, it is of no use.

 

I do not know the context. We have 3 RTL components (wrappers) and multiple test/verification pieces.

  1. The Slave APB wrapper which is layered up using full_wrapper and slave_wrapper. This is the slave when you have a core processor.
  2. The Slave Autonomous wrapper which is layered up from slave_wrapper. This is the Slave when you do not use a core processor.
  3. The Master wrapper which embeds the Master and Slave, both APB, since it can switch back and forth in roles (or be configured to be just one of the two). This is used with a processor.

 

The test options include:

  1. The SV verification bench which has a master model in test/test_bench and then sets of tests under test/tests, including the autonomous and APB and so on.
  2. The Synopsis VIP which is a UVM bench and was brought up with our Slave APB RTL by T&O for the Venus project.
  3. The Cadence VIP which is a UVM bench and was connected to our RTL by Cadence; I am not sure if we have this in house.
  4. The Avery Design VIP which they have connected to all three components (Master, APB Slave, and autonomous Slave) as I understand. We have rights to this but maybe for a fee.
  5. We have an FPGA port running on an Arty board (so Xilinx Artix-7) with Master and multiple slaves, including autonomous and APB slave.

Hi Renee,

Is it any way (such as purchase) to get the full I3C Slave pack?

With the latest download pack, a few RTL files are missing.

- i3c_hdr_ddr_slave.v (RTL - option)

- i3c_time_control.v (RTL)

- tst_i3c_master_model.v (model)

Purchase the I3C Slave IP is one of options so we just had a meeting with Synopsys.

Synopsys will install an I3C Slave IP evaluation pack in next week.

It will be great if we can get a full I3C Slave evaluation pack from NXP as well.

Thank you so much.

Best Regards,

Joey

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