t2081 SGMII ethernet is not working in uboot

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t2081 SGMII ethernet is not working in uboot

3,447 Views
arumilli
Contributor I

Hello,

I am working on T2081 custom board and connected SGMII interface to the FM1@DTSEC6 with SERDES protocol(SERDES1). I already set the mac and IP address, when I am pinging its not working .

ping failed; host 10.10.40.10 is not alive

Here I am using SRDS_PRTCL_S1(128-135)

Here I attached the log file and RCW

Reset Configuration Word (RCW):
00000000: 120c0017 15000000 00000000 00000000
00000010: de000002 00008000 ec027000 c1000000
00000020: 00000000 00000000 00000000 000387fc
00000030: 00000000 00000000 00000000 00000004

Regards,

Ravindra

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9 Replies

3,375 Views
arumilli
Contributor I

Hello,

Ping is successful when using the RGMII Ethernet interface, but it fails when switching to the SGMII interface.

 

Thanks,

Ravindra

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3,354 Views
Oswalag
NXP TechSupport
NXP TechSupport

I understand.

Please share the complete log starting from u-boot, then, performing both test to investigate more. 

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3,321 Views
arumilli
Contributor I

Hello,

Here i attached the full log file and test results of uboot SGMII Ethernet

We configured PHY into SGMII Mode 

=> mii read 1 0x14 
0001

 

Regards,

Ravindra

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3,245 Views
Oswalag
NXP TechSupport
NXP TechSupport

Please share your RCW configuration file, the serdes configuration for both modules selected and please confirm if you did strictly follow the recommendations given in T2080RM, Section 19.6.1 for SGMII initialization.

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3,228 Views
arumilli
Contributor I
Dear Oswalag,
 
Please find the RCW below - 
 
120c0017 15000000 00000000 00000000
de000002 00008000 ec027000 c1000000
00000000 00000000 00000000 000387fc
00000000 00000000 00000000 00000004
 
We are following the procedure given in TRM and implemented in the function "dtsec_configure_serdes" in u-boot fm/eth.c file. We cross verified the implementation of this function with TRM.
 
In our implementation, we are using the following lane-to-slot assignments in the enclosed eth_t208xqds.c file. 
     static u8 lane_to_slot[] = {1, 1, 1, 1, 2, 3, 4, 7}; 
Is this OK?
 
 
Also, we read in the TRM the following sentence in section 19.5.8 SGMII MDIO Memory Map/Register Definition.
             "The SGMII MDIO register space is selected when the associated SGMIInCR1[MDEV_PORT] matches the Ethernet MAC PHY address (MDIO_CTL[PHY_ADDR])."
We could not find any reference to MDIO_CTL and how to set this value. In our case, PHY address is 1. Can you please give some guidance on how to set this value. 
 
Regards,
Ravindra
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3,188 Views
arumilli
Contributor I

Dear Oswalag,

Introduction
We are using marvel 88E1512 phy chip in sgmii mode for serdes 1 lane H connected to mac6.
we are able to read the phy registers using mdio phy registers.
upon reading register page 1 register 17
we are getting value 0x6000 (serdes powered on) and value 0x6010 (serdes power down).
Register Bit definition attached.
>> Below Attach Register Bit Definition

Attached is the dump for the process serdes registers.
>> Below Attach the registers in text file.

Questions
1) We are not seeing sync status bit set in the PHY.
We would to understand from the processor side how to know the SGMII status ?
2) We want to know how to read MDIO Slave Registers from U-Boot, Can you point us for the same ?
3) Can you give some pointers to know if the serdes Lane-H is configured in SGMII mode correctly ?

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2,973 Views
arumilli
Contributor I

I am working with an SGMII interface and encountering some issues when reading the MDIO registers. Below are the values I've retrieved from the SGMII MDIO registers:

 

- Register 0: 0x1140

- Register 1: 0x9

- Register 2: 0x83

- Register 3: 0xffff (reading this register gives an error)

- Register 4: 0x1

- Register 5: 0x0

- Register 6: 0x4

- Register 7: 0x0

- Register 8: 0x0

- Register 9: 0x0

- Register 10: 0x0

- Register 11: 0x0

- Register 12: 0x0

- Register 13: 0x0

- Register 14: 0x0

- Register 15: 0x0

- Register 16: 0x0

- Register 17: 0x1

- Register 18: 0xd40

- Register 19: 0x3

- Register 20: 0x3

 

**Question 1:**

When reading the SGMII PHY Identifier Lower register (MDIO_SGMII_PHY_ID_L - 0x3), I am receiving 0xffff. Is this a valid value, or does it indicate an issue with the PHY communication?

 

**Question 2:**

When reading the SGMII status register (MDIO_SGMII_SR), the LINK_STAT bit is always 0, indicating an invalid link. What could be causing this issue? Could it be related to the PHY configuration, or is there a potential hardware issue?

 

Any guidance or insights into these issues would be greatly appreciated.

 

Thank you in advance for your help!

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3,395 Views
Oswalag
NXP TechSupport
NXP TechSupport

 

Hello,

Are you able to ping from U-Boot(T2081) to your PC?

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3,261 Views
arumilli
Contributor I

Hello,

Here i attached the full log file and test results of uboot SGMII Ethernet

We configured PHY into SGMII Mode 

=> mii read 1 0x14 
0001

 

Regards,

Ravindra

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