Dear Oswalag,
Please find the RCW below -
120c0017 15000000 00000000 00000000
de000002 00008000 ec027000 c1000000
00000000 00000000 00000000 000387fc
00000000 00000000 00000000 00000004
We are following the procedure given in TRM and implemented in the function "dtsec_configure_serdes" in u-boot fm/eth.c file. We cross verified the implementation of this function with TRM.
In our implementation, we are using the following lane-to-slot assignments in the enclosed eth_t208xqds.c file.
static u8 lane_to_slot[] = {1, 1, 1, 1, 2, 3, 4, 7};
Is this OK?
Also, we read in the TRM the following sentence in section 19.5.8 SGMII MDIO Memory Map/Register Definition.
"The SGMII MDIO register space is selected when the associated SGMIInCR1[MDEV_PORT] matches the Ethernet MAC PHY address (MDIO_CTL[PHY_ADDR])."
We could not find any reference to MDIO_CTL and how to set this value. In our case, PHY address is 1. Can you please give some guidance on how to set this value.
Regards,
Ravindra