how to make pbl integrated uboot image which used to boot from nand flash

[liujianbo]

About the uboot Image which used to burn into nand flash on T2080 target, it include rcw, pbl and uboot, based on my understanding of boot sequence, only first 8k of flash will be copied into sram firstly, then run some pbi etc.. command to setup init env.

But check the PBI command in this image, we found the pbi's CRC command(0x13_8040: PBI CRC check command) will end in address 0x2A908, it's far away from the first 8k, looks PBL can not be copied to sram completely, if we use the wrong image for nand flash booting?

The image I used is came from build_t2080rdb-64b/tmp/work/t2080rdb_64b-fsl-linux/u-boot-qoriq/2016.01+fslgit-r0/git/T2080RDB_NAND_config/u-boot-with-spl-pbl.bin

/***************************************/
000000: aa55 aa55 010e 0100 1005 0013 0800 0000  .U.U............
0000010: 0000 0000 0000 0000 6c2d 0002 f010 4200  ........l-....B.
0000020: fc02 7000 a100 0000 0000 0000 0000 0000  ..p.............
0000030: 0000 0000 0001 9000 0000 0000 8000 0004  ................
0000040: 0000 0000 0000 0004 0901 0000 0020 0400  ............. ..
0000050: 0913 8000 0000 0000 0913 80c0 0000 0100  ................
0000060: 0901 0100 0000 0000 0901 0104 fff8 0009  ................
0000070: 0901 0f00 0800 0000 0901 0000 8000 0000  ................
0000080: 0900 0d00 0000 0000 0900 0d04 fff8 0000  ................
0000090: 0900 0d08 8100 0012 0911 0000 8000 0403  ................
00000a0: 0911 0020 2d17 0008 0911 0024 0010 0008  ... -......$....
00000b0: 0911 0028 0010 0008 0911 002c 0010 0008  ...(.......,....
00000c0: 094f c030 0000 8148 094f d030 0000 8148  .O.0...H.O.0...H
00000d0: 0900 0010 0000 0000 0900 0014 ff00 0000  ................
00000e0: 0900 0018 8100 0000 0913 8000 0000 0000  ................
00000f0: 0913 80c0 0000 0000 81fd 8000 2705 1956  ............'..V
0000100: 552d 426f 6f74 2032 3031 362e 3031 322e  U-Boot 2016.012.
0000110: 302b 6761 3962 3433 3766 2028 4175 6720  0+ga9b437f (Aug
...........
002a8d0: 0000 0000 0000 0000 0000 0000 0000 0000  ................
002a8e0: 0000 0000 0000 0000 0000 0000 0000 0000  ................
002a8f0: 0000 0000 4bff f004 0913 8000 0000 0000  ....K...........
002a900: 0913 80c0 0000 0000 0813 8040 3475 4866  ...........@4uHf
/***************************************/

[yipingwang]

Hello Jianbo,

You use the correct u-boot image, PBL(RCW+PBI) is deployed before the address 0000100 in the u-boot image.

Have a great day,
Yiping

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[liujianbo]

Hi Yiping:

Thanks for your updates!

After burn this image into flash, via Code Warrior tool, we can see u-boot-spl worked well, we continue debug into the second u-boot ,  refer the doc: AN 4876: Chapter 6.3 "U-Boot Nand ramboot debugging".

1, set PIC load address to 0x200000, and set hw breakpoint to 0x200008

2, reset target will let uboot stop at 0x200008, here u-boot should have run in DDR RAM.

3, then I can do single step debug, but u-boot will always step into TLBError Exception in "write_new_ccsrbar"(after finish the second sync instruction):

/****************************************************************************/

write_new_ccsrbar:
        lis     r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
        ori     r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
        lis     r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
        ori     r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
        lis     r2, CCSRAR_C@h
        ori     r2, r2, CCSRAR_C@l

        stw     r0, 0(r9)       /* Write to CCSRBARH */
        sync                    /* Make sure we write to CCSRBARH first */
        stw     r1, 4(r9)       /* Write to CCSRBARL */
        sync

/****************************************************************************/

Comparing the reference board, custom board did no use DIMM DDR RAM, to support this kind of DIMM DDR RAM, I did the following modification:

1,  disable "#define CONFIG_DDR_SPD" in $(root_uboot)/include/configs/T208xRDB.h

2, add DDR configuration in $(root_uboot)/include/configs/T208xRDB.h, refer to other board configuration which did not use DIMM either.

/***************************************************************************/

#define CONFIG_SYS_SDRAM_SIZE           2048
#define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
#define CONFIG_SYS_DDR_CS0_BNDS         0x0000007F
#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
#define CONFIG_SYS_DDR_CS1_BNDS         0x008000BF
#define CONFIG_SYS_DDR_CS1_CONFIG       0x00000202
#define CONFIG_SYS_DDR_TIMING_3         0x010C1000
#define CONFIG_SYS_DDR_TIMING_0         0x4044000C
#define CONFIG_SYS_DDR_TIMING_1         0xA8A00C45

.......

/***************************************************************************/

To dig the root cause of this kind of issue, do you have some suggestion?  For the second u-boot have begin run in DDR, if TLB setting might still have some problem?

By the way, to support non-DIMM DDR, the above modification is correct, these modification can be implied into both u-boot(spl and the second u-boot)?

And I look through another doc about u-boot debug: CodeWarrior Development Studio for Power Architecture Processors Targeting Manual, Chapter 7.6.4.4 "Debugging U-Boot using Nand flash", it mentioned that we need run some uboot_36_stagen_preparation.tcl script before get into the next stage, but I failed to find these script in Code Warrior 10.5's installation, do you have some comments on this doc's description?

Many thanks for your time!!

[yipingwang]

Hello Jianbo,

Please refer to board/freescale/t208xrdb/ddr.c, DDR controller is initialized using SPD for T2080RDB.

If you use fixed SDRAM parameters setting, please refer to the file board/freescale/p1010rdb/ddr.c.

Have a great day,
Yiping

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[liujianbo]

Hi  Yiping:

Thanks for your kindly reply!!

About DDR init on PA, under my understanding, rcw and pbi will setting it's hardware character(such as working frequency etc.), u-boot-spl will do controller config(ddr.c) and needed LAW/TLB setting(start.S), after switch to RAM, the second u-boot will re-do these init job again.

If my understanding is correct, when do debuing via codewarrior, if we have done controller config in hardware init script(T2080RDB-PCIe_init_core.tcl), we can disable this part(ddr.c) in u-boot-spl and the second u-boot, let them share the DDR controller setting in init script?

[yipingwang]

Hello Jianbo,

Please refer to the following NAND boot procedure.

PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. SPL further initializes DDR using SPD or DDR controller parameters and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. Finally SPL transers control to u-boot for futher booting.

It seems that I didn't understand your purpose totally. Your purpose of debugging u-boot is to debug u-boot code to make it work normally. If you only want to verify DDR controller initialization parameters, please just create a bareboard project to verify whether the sample program could be executed normally in DDR.

Have a great day,
Yiping

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[liujianbo]

Hi Yiping:

Thanks for your help patiently!

And sorry for my unclear description, here given some more info on my question:

1, because we use fixed DDR instead of DIMM on custom board, we need to change some DDR controller setting, after modify hw init script(T2080RDB-PCIe_init_core.tcl), it can run application normally on DDR in a RAM project of CW.

2, in u-boot-spl, I refer to the codes of p1010 under your suggestion, and re-implement initdram() function(board/freescale/t208xrdb/ddr.c):

3, but in fixed_sdram() codes which came from p1010rdb bsp, u-boot-spl will enable CONFIG_SYS_RAMBOOT config, it will not  call fsl_ddr_set_memctl_regs(), but return SDRAM_SIZE directly:

/***************************************************************/

phys_size_t fixed_sdram(void)
{
        int i;
        char buf[32];
        fsl_ddr_cfg_regs_t ddr_cfg_regs;
        phys_size_t ddr_size;
        ulong ddr_freq, ddr_freq_mhz;
        struct cpu_type *cpu;

#if defined(CONFIG_SYS_RAMBOOT)
        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif

        ddr_freq = get_ddr_freq(0);
        ddr_freq_mhz = ddr_freq / 1000000;

/***************************************************************/

4, it will let the second u-boot trigger TLB Instruction Error exception in create_ccsr_new_tlb section

5, I'm not sure if it's right behavior, and eager  to know if u-boot can run normally on custom board, so I think since hw init script can init DDR correctly(verified via CW RAM project), if we can bypass the DDR init in u-boot-spl and let the second u-boot copy to DDR and run in it?

I failed when disable initram() function boldly, I guess there should be some further action after disable initram in u-boot-spl, still working on it now...

[yipingwang]

Hello Jianbo,

Please refer to board/freescale/corenet_ds/ddr.c and board/freescale/corenet_ds/p4080ds_ddr.c for how to initialize DDR controller with fixed parameters.

Have a great day,
Yiping

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