eSPI status bits in SPIE do not keep up with FIFO state

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eSPI status bits in SPIE do not keep up with FIFO state

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dheyse
Contributor I

I'm trying to use the eSPI in polling mode to access a device connected to SPI CS1 on a T1042 RDB devkit and I'm having issues monitoring the TX FIFO status bits in the SPIE register.  In particular, I've noticed that bytes added to the FIFO do not show up right away in the SPIE TXCNT and TNF status fields.  For example, if I fill the FIFO with 32 bytes in preparation for starting a transmit frame and then read the SPIE, I see TNF is still set and TXCNT is 6 or 7 instead of 0.  Eventually a subsequent SPIE read will show the correct values.  Is there any information on how long I should wait after writing to the FIFO before the status in the SPIE is up to date?

This becomes more of an issue once the frame starts transmitting and I have to keep the FIFO fed, because I don't want to overfill the FIFO (and lose data) by reading SPIE too quickly and having it say there's still space in the FIFO when it its actually full.

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dheyse
Contributor I

Hi Pavel,

Thanks for the example code.  I'm not sure it answers my question, but I can see the send_get_bytes* functions in eSPI.zip do look fairly safe from TX FIFO overflows.  However it seems like a waste of the FIFO to insert only one byte and then immediately wait for the FIFO to empty out before proceeding.  Is there a reason for this?  Also, why does it have to check that both TXCNT is 32 and TXE is set?  Shouldn't one or the other be sufficient to let you know the TX FIFO is empty?  And what happens if the the code is interrupted and TX FIFO remains empty for a while.  Does the eSPI give up with an underrun, or send a dummy character, or does it hold the clock and resume when the TX FIFO eventually gets fed?

https://community.nxp.com/thread/463168 mentions AN3904 which has detailed information on these sorts of questions for an older chip.  I was hoping for a pointer to something like that for the eSPI in the QorIQ chips.

For my original question.  The T1040 Reference Manual says:

The eSPI core handshake protocol can be implemented by using a polling or interrupt mechanism. When using a polling mechanism, the core reads the SPIE in a predefined frequency and acts according to the value of the SPIE bits. The polling frequency depends on the eSPI serial channel frequency.

 

So I'm interested in a little more detail on the relationship between the "predefined frequency" at which I'm supposed to poll the SPIE and the eSPI serial channel frequency.  If the channel frequency is 25MHz, does that mean I should only expect the SPIE to be updated on 25MHz intervals?

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Pavel
NXP TechSupport
NXP TechSupport

Look at attached files. These files contains simple program example for eSPI and eSPI driver from SDK 2.0.

Use these files as example.


Have a great day,
Pavel Chubakov

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