What is present on IFC_A[n:31] with address shifted left

[scottgerhold]

If with the T2080 I have CSORn[ADM_SHFT]=5 and ADM MODE=0 it should appears as it matches Figure 13-7 in the T2080 Reference Manual. However in the text just above the figure is this statement "The least significant bit (LSB) can be retrieved from the ADDR bus. ADDR[31] will carry the lsb of the system address. That doesn't quite seem to match Figure 13-7.  What exactly will be on ADDR[27:31] in the mode described by Figure 13-7? Will it still contain the LSBs unshifted?

Specifically I have a 16-bit wide data bus to the device. I was planning to set ADM_SHFT_MODE = 0 and ADM_SHFT = 01010 (10) and provide the upper 16 address bits (A10:A25) on IFC_AD[0:15] and connect IFC_A[26:30] as the LSB to the device. This was based on the statement about ADDR[31] always having the lsb on it and from that I then jumped to the conclusion that the other LSBs would still be mapped to their respective pins when not in conflict with the shifted address. Should I instead be using AFC_A[16:20] or will either work?

[r8070z]

The T2080 RM Figure 13-7 is not suitable for the T2080. Right before the figure the manual says

“For a chip that has a 16-bit AD bus and an 11-bit ADDR bus, which needs to be

interfaced with a memory of 8-bit port width and 128 MB memory size (requiring a 27-

bit address), the following figure shows how system address bits are placed during IFC

address phase (AVD/ALE assertion) with a CSORn[ADM_SHFT] value of 5.”.

I guess you use 32-bit addressability. Unfortunately the T2080 RM has a typo in the IFC_CSORn_NOR field descriptions, ADM_SHFT. Instead of “cfg_rcw_src[6:7]=00 (00 22b addressability) then ADM_SHFT = 10”

there is has to be

“if cfg_rcw_src[6:7]=11 (11 32b addressability) then ADM_SHFT = 00”.

It is right for your case. Because 16 lsb bits on the A[16:31] you should not shift the msb bits on the LAD[0:15]. For 16-bit device connect IFC_A[16:30] as the LSB to the device. 

[scottgerhold]

I am not sure I understand the answer you provided. I am not concerned with what the rcw source is set up for. I am not accessing this device during the boot phase. I am concerned with operation after SW starts executing and we set up the IFC bus CS the way I need it at that time. 

The configuration I am concerned with is to connect to an FPGA with a 16-bit bus and to minimize the number of IFC_ADDR[] bits I attach to to only use 5 bits (enough for a single cache line). I only need 21 bits of address. In that configuration I desire that the 16 address bits from IFC_AD[0:15] concatenated with the 5 bits I get from IFC_A are contiguous. In other words IFC_AD[15] represents the next address bit after the upper UFC_A[x] I connect to (no gaps in addressing). Thus I need to know if I connect to IFC_AD[0:15] & IFC_A[26-30] or IFC_AD[0:15] & IFC_A[16:20] to get 21 bits of address I need.

I think Figure 13-7 does match the text immediately above it, just not the text in the paragraph that is the 3 paragraphs above it. Figure 13-7 doesn't necessarily have anything to do with the rcw boot mode.

[r8070z]

Dear, Scott Gerhold

Actually I did not get what you want. Now I see, you want use only IFC_A[26-30] from IFC_A[16-31]. I supposed that you can use IFC_A[16-30], sorry. Yes, when ADM_SHFT_MODE = 0 and ADM_SHFT = 01010 (10) you can get the [10:25] address bits from IFC_AD[0:15] concatenated with the [26:30] address bits from IFC_A[26-30] for your 16-bit device.