Use of TLB

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Use of TLB

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Contributor II

Hi. Please help me to understand the TLB(translation Look-aside Buffer) hardware in a processor. What so far I know that TLB is a kind of cache memory integrated into the processor chip. Whenever CPU try to access any virtual memory first CPU looks into TLB cache. If there is entry for that virtual address then corresponding physical page no is used for physical memory. If No entry for that virtual address in TLB then the CPU will consult the page table entry. What is the use of TLB entries in the following uboot code. please share your knowledge.

struct fsl_e_tlb_entry tlb_table[] = {
    /* TLB 0 - for temp stack in cache */
    SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
              CONFIG_SYS_INIT_RAM_ADDR_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 0, BOOKE_PAGESZ_4K, 0),
    SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
              CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 0, BOOKE_PAGESZ_4K, 0),
    SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
              CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 0, BOOKE_PAGESZ_4K, 0),
    SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
              CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 0, BOOKE_PAGESZ_4K, 0),

    /* TLB 1 */
    /* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
    /*
     * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
     * SRAM is at 0xfff00000, it covered the 0xfffff000.
     */
    SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
    /*
     * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
     * space is at 0xfff00000, it covered the 0xfffff000.
     */
    SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
              CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
              0, 0, BOOKE_PAGESZ_1M, 1),
#else
    SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 0, BOOKE_PAGESZ_4K, 1),
#endif

    /* *I*G* - CCSRBAR */
    SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 1, BOOKE_PAGESZ_16M, 1),

    /* *I*G* - Flash, localbus */
    /* This will be changed to *I*G* after relocation to RAM. */
    SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
              MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
              0, 2, BOOKE_PAGESZ_256M, 1),

#ifndef CONFIG_SPL_BUILD
    /* *I*G* - PCIe 1, 0x80000000 */
    SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 3, BOOKE_PAGESZ_512M, 1),

    /* *I*G* - PCIe 2, 0xa0000000 */
    SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 4, BOOKE_PAGESZ_256M, 1),

    /* *I*G* - PCIe 3, 0xb0000000 */
    SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 5, BOOKE_PAGESZ_256M, 1),


    /* *I*G* - PCIe 4, 0xc0000000 */
    SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 6, BOOKE_PAGESZ_256M, 1),

    /* *I*G* - PCI I/O */
    SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 7, BOOKE_PAGESZ_256K, 1),

    /* Bman/Qman */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
    SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 9, BOOKE_PAGESZ_16M, 1),
    SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
              CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 10, BOOKE_PAGESZ_16M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
    SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 11, BOOKE_PAGESZ_16M, 1),
    SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
              CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
    SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
    /*
     * *I*G - NAND
     * entry 14 and 15 has been used hard coded, they will be disabled
     * in cpu_init_f, so we use entry 16 for nand.
     */
    SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 16, BOOKE_PAGESZ_64K, 1),
#endif
#ifdef CONFIG_SYS_CPLD_BASE
    SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 17, BOOKE_PAGESZ_4K, 1),
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
    /*
     * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
     * fetching ucode and ENV from master
     */
    SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
              CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
              0, 18, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
    SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
              MAS3_SX|MAS3_SW|MAS3_SR, 0,
              0, 19, BOOKE_PAGESZ_2G, 1)
#endif

};

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NXP TechSupport
NXP TechSupport

Your statements regarding TLB operation are generally correct. TLBs,
their organization, operation and software model are described in
e6500 Core Reference Manual, Chpater 6. Refer to that document for
technical details.

Regarding u-Boot, it does not implement multitasking or dynamically
mapped virtual memory. Rather, it creates static TLB mappings for
the physical addresses it needs to perform it's tasks. The code
you quoted creates a table of virtual to physical address mappings which
are then programmed into TLBs in init_tlbs() defined in
/arch/powerpc/cpu/mpc85xx/tlb.c
SET_TLB_ENTRY macro is defined in arch/powerpc/include/asm/mmu.h
Each invocation creates a mapping for a physical address region
that belongs to a peripheral. I'm not going to explain every macro
here, there are too many of them, most are pretty self-explanatory.
For instance,


SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 0, BOOKE_PAGESZ_1M, 1),
              
creates a mapping for the on-chip SRAM.

SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
              MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
              0, 17, BOOKE_PAGESZ_4K, 1),
              
maps the board CPLD registers.    

Most (if not all) of the macros starting with CONFIG_SYS_* are defined in the
board configuration header. See comments in that file for
explanations. Grep the source code for other used macros to see
their meaning or ask more specifically.


Have a great day,
Platon

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