Hello,
I have a working design with the T1040 UMCC, using several channels on a 128 timeslot bus connected to TDMA.
The TDMA interface of the T1040 connects to an FPGA on my design.
We have used the MCC QUICC peripheral on prior designs, and there was never any issue with the data alignment on the TDM bus, relative to frame syncs, TSYNC and RSYNC.
For these prior designs, the MCC uses the SI TSA interface in MCC mode. Whereas for the UMCC, the SI TSA simply assigns all the used timeslots to the UCC running in UMCC mode, and the UMCC uses its routing tables to direct the data to the appropriate channel.
In order to get our present design to work using the UMCC, the FPGA had to compensate for the alignment of the timeslots to the TDM bus.
For the T1040 TDM to FPGA direction, there was a 19-bit shift relative to the frame sync (TSYNC) required.
For the FPGA to T1040 TDM, there was a 3-bit shift relative to RSYNC required.
Is there any means for adjusting this within the UMCC or SI peripheral to eliminate these shifts relative to the frame sync's?
Regards,
Matt
