The DDR memory controller address of T1024 cannot be accessed in uboot.

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The DDR memory controller address of T1024 cannot be accessed in uboot.

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wangmeng0427
Contributor II

Hi all,

I found the DDR memory controller registers(start from 0xfe008000) cannot be accessed in U-boot. If they are accessed, the booting would be stopped. I tried to access the I2C(from 0xfe118000) and other addresses(0xfe000000~0xfe010000, except 0xfe008000~0xfe009000), and the operation can successfully.

And I print the TLB and LAW, but don't found any wrong. Can you give some help? Thanks very much.

TLBCAM entries
entry 00: V: 1 EPN 0xfffc0000 RPN 0xfffc0000 size:256 KiB
entry 01: V: 1 EPN 0xfe000000 RPN 0xfe000000 size:16 MiB
entry 02: V: 1 EPN 0xe0000000 RPN 0xfe0000000 size:256 MiB
entry 03: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 04: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 05: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 06: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 07: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 08: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 09: V: 1 EPN 0xf0000000 RPN 0xf00000000 size:4 MiB
entry 10: V: 1 EPN 0xff800000 RPN 0xfff800000 size:64 KiB
entry 11: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 12: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 13: V: 0 EPN 0xfe000000 RPN 0xfe000000 size:4 KiB
entry 14: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 15: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 16: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 17: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 18: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 19: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 20: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 21: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 22: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 23: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 24: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 25: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 26: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 27: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 28: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 29: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 30: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 31: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 32: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 33: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 34: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 35: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 36: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 37: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 38: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 39: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 40: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 41: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 42: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 43: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 44: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 45: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 46: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 47: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 48: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 49: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 50: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 51: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 52: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 53: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 54: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 55: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 56: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 57: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 58: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 59: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 60: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 61: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 62: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB
entry 63: V: 0 EPN 0xfffff000 RPN 0xfffff000 size:4 KiB

Local Access Window Configuration
LAWBARH00: 0x0000000f LAWBARL00: 0xf4000000 LAWAR00: 0x81800018
(EN: 1 TGT: 0x18 SIZE: 32 MiB)
LAWBARH01: 0x0000000f LAWBARL01: 0xf6000000 LAWAR01: 0x83c00018
(EN: 1 TGT: 0x3c SIZE: 32 MiB)
LAWBARH02: 0x0000000f LAWBARL02: 0x00000000 LAWAR02: 0x81d00015
(EN: 1 TGT: 0x1d SIZE: 4 MiB)
LAWBARH03: 0x0000000f LAWBARL03: 0xff800000 LAWAR03: 0x81f0000f
(EN: 1 TGT: 0x1f SIZE: 64 KiB)
LAWBARH04: 0x00000000 LAWBARL04: 0x00000000 LAWAR04: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH05: 0x00000000 LAWBARL05: 0x00000000 LAWAR05: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH06: 0x00000000 LAWBARL06: 0x00000000 LAWAR06: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH07: 0x00000000 LAWBARL07: 0x00000000 LAWAR07: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH08: 0x00000000 LAWBARL08: 0x00000000 LAWAR08: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH09: 0x00000000 LAWBARL09: 0x00000000 LAWAR09: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH10: 0x00000000 LAWBARL10: 0x00000000 LAWAR10: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH11: 0x00000000 LAWBARL11: 0x00000000 LAWAR11: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH12: 0x00000000 LAWBARL12: 0x00000000 LAWAR12: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH13: 0x00000000 LAWBARL13: 0xfffc0000 LAWAR13: 0x81000011
(EN: 1 TGT: 0x10 SIZE: 256 KiB)
LAWBARH14: 0x00000000 LAWBARL14: 0x00000000 LAWAR14: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH15: 0x00000000 LAWBARL15: 0x00000000 LAWAR15: 0x00000000
(EN: 0 TGT: 0x00 SIZE: 2 Bytes)

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ufedor
NXP Employee
NXP Employee

> The board can bring up with another boot loader.

The DDR controller CCSR registers access failure can't be caused by a software issue.

Ensure that the same RCW is used for the previous and current bring-ups.

Compare values of the DCFG_CCSR_RCWSRn for the different bring-ups.

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6 Replies
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ufedor
NXP Employee
NXP Employee

1) It is required to check the processor connection and ensure (using a digital scope) that all notes in the QorIQ T1024, T1014 Data Sheet, Table 1. Pinout list by bus are fulfilled.

2) Which RCW is used (binary image or U-Boot log).

3) What is the DCFG_CCSR_DEVDISR5 value?

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wangmeng0427
Contributor II

Hi ,

Thanks for your reply.

1) It is required to check the processor connection and ensure (using a digital scope) that all notes in the QorIQ T1024, T1014 Data Sheet, Table 1. Pinout list by bus are fulfilled.

Meng: It should be OK. 

2) Which RCW is used (binary image or U-Boot log).

Meng: I boot from Nand flash. u-boot-with-spl-pbl.bin

3) What is the DCFG_CCSR_DEVDISR5 value?

Meng: Sorry, where can I get the value?

 

By the way, I checked the datasheet and found " Dynamic power management mode " in chapter: DDR Memory Controller. Is there any relation about the issue?

Thanks very much again.

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ufedor
NXP Employee
NXP Employee

1) You wrote:

> It should be OK. 

Is this a new design bring-up?

3) Please refer to the QorIQ T1024 Reference Manual, 7.3.9 Device Disable Register 5 (DCFG_CCSR_DEVDISR5).

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wangmeng0427
Contributor II

Hi,

Thanks very much.

1.Is this a new design bring-up?

Meng: No. The board can bring up with another boot loader. We need bring it up by uboot.

3) Please refer to the QorIQ T1024 Reference Manual, 7.3.9 Device Disable Register 5 (DCFG_CCSR_DEVDISR5).

Meng: I read the related registers: 0xfe0e0070~80. The 0xfe0e0070 is 0x200, and the other are 0 . 

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ufedor
NXP Employee
NXP Employee

> The board can bring up with another boot loader.

The DDR controller CCSR registers access failure can't be caused by a software issue.

Ensure that the same RCW is used for the previous and current bring-ups.

Compare values of the DCFG_CCSR_RCWSRn for the different bring-ups.

1,313 Views
wangmeng0427
Contributor II

Hi 

You are right! The RCW need be modified. After modifying the RCW, the DDR control register can be accessed.

Thanks very much. 

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