T4241, unable to detect NAND Flash

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T4241, unable to detect NAND Flash

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immbalu
Contributor II

Hello,

We are using Nand flash with part no: MT29F128G08CBCEB. 

IFC_CS1_B/GPIO2_10 of IFC INTERFACE is connected to CE0_0# and CE1_0# of nand flash.

IFC_CS2_B/GPIO2_11 of IFC INTERFACE is connected to CE0_1# and CE1_1# of nand flash.

Followed the instructions as per https://community.nxp.com/t5/Layerscape-Knowledge-Base/IFC-Controller-Configuration-on-QorIQ-Custom-... and configured the flash with the following parameters in u-boot.

updated the excel values as per the data sheet parameters

SNoMemory ModeltclstcstwptdhtwhtrrtrptreatrehtwhrtwbtadltrctwctrhzpagePerBlockpageDataSizepageSpareSizeMLCdevicedataioBlockCountEDOtrhoh (toh)trlohtrp(mod)tww
1MT29F128G08CBCEB50705051120504030120200150100100200512163842208188192500050100

 

S.No.Register ->FTIM0FTIM1FTIM2FTIM3Data EyeFTIM0FTIM0FTIM1FTIM1FTIM2FTIM2CSPR0CS0RNandMonCSPR0CSOR  
Memory ModelTCCSTTWPTWCHTTWHTADLETWBETRRTRPTRADTREHTWHRETWW NB0NB1NB2NB3[0:31]NB0NB1NB2NB3[0:31][0:31][0:31][0:31][0:31][16:31]RALPGSSPRZPBTreaPSTHRZ  
1MT29F128G08CBCEB730244063724151036 20E1E02040E1E0204283F0718283F071801E0502401E05024008301111111001401011  


#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CS2_BASE 0xff810000
#define CONFIG_SYS_NAND_CS2_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_CS2_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)

#define CONFIG_SYS_NAND_CS2_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CS2_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_CS2_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)

#define CONFIG_SYS_NAND_AMASK IFC_AMASK(512*1024*16)

#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Bytes */ \
| CSOR_NAND_PGS_8K /* Page Size = 16K as per nand datasheet*/ \
| CSOR_NAND_SPRZ_CSOR_EXT /* Spare size */\
| CSOR_NAND_PB(512)) /*Page Per Block = 512*/

#define CONFIG_SYS_NAND_CSOR_EXT 0x000008A0

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params with reference to RDB*/
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x1E) | \
FTIM0_NAND_TWCHT(0x02) | \
FTIM0_NAND_TWH(0x04))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
FTIM1_NAND_TWBE(0x3F) | \
FTIM1_NAND_TRR(0x07) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x24))
#define CONFIG_SYS_NAND_FTIM3 0x0

#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE,CONFIG_SYS_NAND_CS2_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE (8192 * 1024)

 

Getting "Failed to detect ONFI extended param page" Error from U-Boot.

Here are prints from u-boot

 

 

 

U-Boot 2016.01-19722-ga9b437f-dirty (Jan 12 2022 - 15:47:53 +0530)

CPU0:  T4241, Version: 2.0, (0x82400020)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
       CPU4:1800 MHz, CPU5:1800 MHz, CPU6:1800 MHz, CPU7:1800 MHz,
       CPU8:1800 MHz, CPU9:1800 MHz, CPU10:1800 MHz, CPU11:1800 MHz,
       CCB:600  MHz,
       DDR:800  MHz (1600 MT/s data rate) (Asynchronous), IFC:150  MHz
       FMAN1: 700 MHz
       FMAN2: 600 MHz
       QMAN:  300 MHz
       PME:   466.667 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 0c080012 0e12120e 00000000 08000000
       00000010: 04360848 30547a00 ec03f000 f9000000
       00000020: 00080000 00000000 00000000 0003f000
       00000030: 00000000 50000000 00000000 00000038
I2C:   ready
Board: T4241, SERDES Reference Clocks:
       SERDES1=125MHz SERDES2=125MHz
       SERDES3=100MHz SERDES4=100MHz
SPI:   ready
DRAM:  Initializing DDR
10 GiB left unmapped
12 GiB (DDR3, 64-bit, CL=11, ECC on)

Value From Fuse Register = 10250

Corresponding value to be Written = 42

VID Write Successfull
Flash: 256 MiB
L2:    2 MiB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000
Corenet Platform Cache: 1.5 MiB enabled
Using SERDES1 Protocol: 1 (0x1)
Using SERDES2 Protocol: 27 (0x1b)
Using SERDES3 Protocol: 1 (0x1)
Using SERDES4 Protocol: 9 (0x9)
fsl_ifc_cmdfunc: error, unsupported command 0x5.
fsl_ifc_read_buf beyond end of buffer (48 requested, 0 available)
fail in the CRC.
Failed to detect ONFI extended param page
No NAND device found
16384 MiB
MMC:   FSL_SDHC: 0
PCIe1: Root Complex, x1 gen1, regs @ 0xfe240000
  01:00.0     - 10ee:7011 - Multimedia device
PCIe1: Bus 00 - 01
PCIe3: Root Complex, no link, regs @ 0xfe260000
PCIe3: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Net:   Fman1: Uploading microcode version 108.4.5
Could not get PHY for FM_TGEC_MDIO: addr 16
Failed to connect
Fman2: Uploading microcode version 108.4.5
FM1@TGEC1, FM2@DTSEC5 [PRIME], FM2@DTSEC6, FM2@DTSEC9, FM2@DTSEC10

POST Start:

POST Complete

 U-boot Software Version : 1.0

 tap env addr 0
Updating Boot Status Successful
Hit any key to stop autoboot:  0
T4241_uboot>

 

 

 

 

Thanks,

Balaji.G

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yipingwang
NXP TechSupport
NXP TechSupport

Please define the following include/configs/T4240RDB.h.

#define CONFIG_SYS_NAND_CSPR_EXT (0xf)

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