T4240: Cannot change to alternative flash boot section

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T4240: Cannot change to alternative flash boot section

1,105 Views
hum
Contributor I

Hello,

we have a T4240RDB board, on which we would like to update U-Boot. Currently there is a QorIQ SDK v1.5 U-Boot installed. We flashed a new SDK v2.0 U-Boot to the alternative boot section. When issued an "qix altbank" command to change to the altenative boot section command nothing happens (see log below). Changes to the board's SW3 DIP switch also has no effect. Always the SDK v1.5 U-Boot gets booted.

Has anyone an idea, how to change to the alternative U-Boot ?

U-Boot 2013.01QorIQ-SDK-V1.5 (Jan 17 2014 - 15:15:08)

CPU0:  T4240E, Version: 2.0, (0x82480020)
Core:  E6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
       CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
       CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667 MHz,
       CCB:733.333 MHz,
       DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN:  366.667 MHz
       PME:   533.333 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Reset Configuration Word (RCW):
       00000000: 16070019 18101916 00000000 00000000
       00000010: 70701050 00448c00 0c020000 f5000000
       00000020: 00000000 ee0000ee 00000000 000287fc
       00000030: 00000000 50000000 00000000 00000028
Board: T4240RDB, SERDES Reference Clocks: SERDES1=100MHz SERDES2=156.25MHz SERDES3=100MHz SERDES4=100MHz
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM 9JSF25672AZ-2G1K1
Detected UDIMM 9JSF25672AZ-2G1K1
Detected UDIMM 9JSF25672AZ-2G1K1
4 GiB left unmapped
    DDR: 6 GiB (DDR3, 64-bit, CL=13, ECC on)
       DDR Controller Interleaving Mode: 3-way 4KB
Flash: 128 MiB
L2:    2048 KB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000
Corenet Platform Cache: 1536 KB enabled
Using SERDES1 Protocol: 28 (0x1c)
Using SERDES2 Protocol: 56 (0x38)
Using SERDES3 Protocol: 2 (0x2)
Using SERDES4 Protocol: 10 (0xa)
SRIO1: disabled
SRIO2: disabled
NAND:  2048 MiB
MMC:  FSL_SDHC: 0
PCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe260000
PCIe3: Bus 01 - 01
PCIe4: Root Complex, no link, regs @ 0xfe270000
PCIe4: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Warning: SERDES2 expects reference clock 125MHz, but actual is 156.25MHz
Net:   Fman1: Uploading microcode version 106.4.10
Failed to connect
Failed to connect
cs4340_phy_init error.
cs4340_phy_init error.
Fman2: Uploading microcode version 106.4.10
cs4340_phy_init error.
cs4340_phy_init error.
FM1@DTSEC1 [PRIME], FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@TGEC1, FM1@TGEC2, FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4, FM2@TGEC1, FM2@TGEC2
Hit any key to stop autoboot:  0
=>
=>
=> qix altbank
=>
=>

Labels (1)
9 Replies

521 Views
hum
Contributor I

Hello Yiping,

changing the SW3 switch settings does not seem to have an effect of changing the boot loader.

We did not yet reprogram anything on the board. We do now want to make an update (mainly of the FMan microcode), but I'm not comfortable programming something in the flash without having a backup to boot from.

The U-Boot also does not know the cpld command.

=> cpld
Unknown command 'cpld' - try 'help'
=> help cpld
Unknown command 'cpld' - try 'help' without arguments for list of all known commands

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Manuel Huber,

I just checked our internal database, please refer to the following.

For T4240RDB, the feature of booting from alternative NOR flash bank is supported since SDK 1.7 release.

In T4240RDB User Guide, you can search for "fbank_sel" to see the support for splitting the NOR flash into tow logical halves. The support for fbank_sel is first available on Rev D boards.

So this feature requires revision D of the T4240RDB.


Have a great day,
Yiping

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521 Views
sareenakp
Contributor II

Hello Yiping,

Even we are trying the same here at our lab. We have a T4240RDB QorIQ SDK v1.5 U-Boot installed. Now we see that the flash map has changed between SDK 1.5 and SDK 2.0. 

Now how do we upgrade the flash map to that of SDK2.0.

Thanks,
Sareena.

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521 Views
sareenakp
Contributor II

Hello Yiping,

The board we have here T4240RDB Rev 2.0 Silicon. How do we know if it is the revision D??

Also in case, it is not revision D, what is the way out to program the SDK 2.0 binaries.

Thanks,

Sareena.

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521 Views
sareenakp
Contributor II

Hello Yiping,

My uboot log is as given below. Does it mean that I have revision E??

U-Boot 2013.01QorIQ-SDK-V1.5 (Jun 05 2014 - 16:58:13)
CPU0: T4240E, Version: 2.0, (0x82480020)
Core: E6500, Version: 2.0, (0x80400120)

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521 Views
scottwood
NXP Employee
NXP Employee

No, the E in T4240E indicates the chip variant that contains a crypto unit.

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521 Views
sareenakp
Contributor II

Dear Scott,

Thank you for the reply.

1) Where can I find the REV of my T4240RDB board?

2) How to program the SDK 2.0 binaries into the T4240RDB that had SDK 1.5 uboot. Can you give me a brief as to how to go about the flash map change.

If needed I can post it as a new question.

Thanks,
Sareena.

521 Views
jakobdanielsson
Contributor II

Dear Sareena, 

Did you ever find an answer to this question?

I'm in the same struggles using a T4240E QDS board

Best,

Jakob

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521 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Manuel Huber,

For board revision T4240RDB-PD, the NOR flash can be split into two logical halves by setting the FBANK_SEL signal. The FBANK_SEL signal is controlled by setting SW3[3].

As normal, users could use "cpld reset altbank" to change to the alternate bank, but I am confusing now, there is no CPLD version information displayed in the u-boot log, did you program CPLD previsously?

Thanks,

Yiping

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