T4240 10GBase-KR configuration

[mikle_samarkin]

Hello everyone!

We have 10G link between FPGA and T4240 through backplane. Now we are trying to configure 10GBASE-KR.

In Reference Manual 18.6.1.3 XFI/10FBase-KR said modified, Transmit Equalization Control Register 0 LNnTECR0, following the procedure in Lane Reset and Reconfiguration. Next no visibility that 10GBase-KR is on. There is no trying Auto-Negotiation or Link-training from T4240. Also reading mdio registers  MDIO_XFI_PMD_CR1 and  MDIO_XFI_10GKR_PMD_CR indicate that 10GBase-KR not enable.

What we need to do, or which registers can help us to figure out our issue?

[mikle_samarkin]

Hello Yiping Wang, thanks for you answer.

Yes, we did exactly as in Reference Manual, but there is no visible action that 10GBase-KR is on.

Meanwhile how we can track in status that 10GBase-KR is on?

[yipingwang]

Hello Mikle,

If you are using Linux SDK, you could refer to 10GBASE-KR Linux Kernel driver in drivers/net/phy/fsl_10gkr.c.

Please refer to the link training procedure addressed in xgkr_wq_state_machine, please refer to the section after  "dev_info(&phydev->dev, "is training.\n")".

Please enable training through XFI 10GBASE-KR PMD Control Register, and check MDIO_XFI_10GKR_PMD_SR, if TRAIN_FAIL, please reset lane then start training again until LT training succeed(or PMD_STATUS_SUP_STAT and PMD_STATUS_FRAME_LOCK) before the dead line.

Thanks,

Yiping

[yipingwang]

Hello Mikle Samarkin,

All default SerDes settings are for XFI. For 10GBase-KR, the following settings need to
be modified, following the procedure.
1. Put the lane(s) into reset by setting SerDesx_LNmGCR0[TRST_B]=0 and
   SerDesx_LNmGCR0[RRST_B]=0.
2. Wait at least 50 ns
3. Change the desired per-lane settings
4. Wait at least 120 ns
5. Take the lane(s) out of reset by setting SerDesx_LNmGCR0[TRST_B]=1 and
SerDesx_LNmGCR0[RRST_B]=1

Thanks,

Yiping