T2081QDS: MMC support seems to be broken by current SW

[ralftruebenbach]

Hello,

I have trouble to get mmc working with Linux at our T2081 board:

~ # mmc0: Timeout waiting for hardware cmd interrupt.
sdhci: =========== REGISTER DUMP (mmc0)===========
sdhci: Sys addr: 0x00000000 | Version:  0x00002002
sdhci: Blk size: 0x00000000 | Blk cnt:  0x00000000
sdhci: Argument: 0x00000000 | Trn mode: 0x00000000
sdhci: Present:  0x01fd0009 | Host ctl: 0x00000020
sdhci: Power:    0x00000000 | Blk gap:  0x00000000
sdhci: Wake-up:  0x00000000 | Clock:    0x00000008
sdhci: Timeout:  0x00000000 | Int stat: 0x00000000
sdhci: Int enab: 0x007f0007 | Sig enab: 0x007f0003
sdhci: AC12 err: 0x00000000 | Slot int: 0x00002002
sdhci: Caps:     0x34fa0000 | Caps_1:   0x00100010
sdhci: Cmd:      0x00000502 | Max curr: 0x00000000
sdhci: Host ctl2: 0x00000000
sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000
sdhci: ===========================================‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Than I found a patch witch seems to be the reason for it (patch is also applied to fsl u-boot):

[U-Boot] [PATCH 3/4] mmc: fsl_esdhc: Add peripheral clock support for kernel  

[U-Boot] [PATCH 4/4] powerpc/t2080qds: enable eSDHC peripheral clock support for kernel 

The Patch sets CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK for T2080 and T2081 (in T208xQDS.h), but CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK is only implemented for T2080.

When I remove CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK from our U-Boot board header MMC is working under Linux.

Than I reenabled CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK and fixed the broken Patch
(see Patch below). But than again mmc is not working anymore. Maybe it's because of my clock frequency settings. I must say that I didn't find any information which settings are valid. At the moment I've set CGA_PLL2 / 4 = 1400MHz / 4 = 350MHz (or do I have to divide again with 2 like when I use the platform clock?).

My Questions:

1. Which frequencies are valid for the mmc (eSDHC)?
2. What is the advantage of using the peripheral clock instead of using the platform clock?

index ea92ff3..e887c01 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -452,7 +452,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define ESDHC_CLK_SEL  0x00000007
 #define ESDHC_CLK_SHIFT        0
 #define ESDHC_CLK_RCWSR        15
@@ -476,7 +476,7 @@ void get_sys_info(sys_info_t *sys_info)
        case 4:
                sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
                break;
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
        case 5:
                sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
                break;
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

[yipingwang]

Hello Ralf Truebenbach,

Please refer to the section "16.4.4.1 Clock generator" in T2080 reference manual. Base clock can be selected by programming ESDHCCTL[PCS]. It selects between platform clock and peripheral clock / 2. Base clock is divided by two of peripheral clocks when PCS=1.

The peripheral clock is defined in RCW[HWA_CGA_M2_CLK_SEL].

The peripheral clock supports higher frequency than platform clock, up to 1G.

On T2080QDS board, we decide to support eMMC HS200 mode, which requires 200MHz SD clock, so peripheral clock needs to be used described in the Reference Manual.

Have a great day,
Yiping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------