We are facing an issue of wrong configuration of T2081 Processor and this issue is intermittent.
Whenever our custom board is powered ON the Processor configures itself with the RCW in the NOR flash. We have configured 1200MHz CPU frequency in the RCW. UART interface is programmed for 115200 baud rate. When the UART interface comes up with 115200 baud rate we are able to see the CPU is configured for 1200MHz of CPU frequency.
Sometimes at power ON the UART is not able to configure at 115200 baud rate and the screen shows junk information. At this point if the RS232 at the PC end is configured for 57600 baud rate I am able to see the display with CPU frequency configured for 2400MHz.
And this change in CPU frequency occurs only at power ON. Once the Processor is configured for a particular frequency and I assert the Poreset pin the same frequency is maintained constantly.
Can someone help me in knowing why and where the configuration is changing on the board?
I am sending the Linux logs for the CPU configured for 1200MHz and 2400MHz frequency as attachment.
Out of 5 boards 2 boards are having the issue of frequency being different than what is configured. Can you please let me know the address of PORPLLSR register?
We have tested flash IC by writing, reading, blank checking and verifying the data. We are able to write and read properly multiple times. Which means the flash IC is working fine.
Read the register CLKCG1HWACSR and we have read HWACLKSEL bits as "0110 CGA PLL2 divide-by-2" instead of "0001 CGA PLL1 divide-by-1" as configured in RCW.
I would like to know why the register is reading wrong values than the values which are programmed in Flash RCW.
> we have read HWACLKSEL bits as "0110 CGA PLL2 divide-by-2"
This could indicate a power-on issue.
Refer to the QorIQ T2081 Data Sheet and check:
- power sequencing
- power supply ramp rate
- supply voltages
- reset initialization signals timings
On our board the core supply is up after around 30ms after our FPGA boots up. Can I add 100ms to 500ms additional delay for the core power to come up after the FPGA boots up along with the IO voltages like 1.8V and 2.5V.
Sending the screenshot of the oscilloscope waveforms as attachment. The waveforms has 4 signals on the screen
1. 1st signal (yellow colour) is for POreset. Poreset is pulled low at the startup. After 2 seconds the POreset is made high. Before POreset is pulled high all the power supplies including the Processor core and IO supplies are high.
2. 2nd signal (green) is for Processor core which takes around 38ms.
3. 3rd signal (blue) is 1.35V
4. 4th signal (pink) is 1.8V
As per the reference module page 223, DUART module works on platform clock/2 Frequency. But whenever the CPU frequency is changed on the console we are observing that the UART interface data rate is also changing. What is the relation between the CPU core clock frequency with the UART module?
I had checked some of the on board voltages. Can you let me know whether the ripple and rise time that I have given below are correct
1. 1.8V (On board measured ripple 40mV and rise time of 2.8ms)
2. 1V (On board measured ripple 38.4mV and rise time of 1.6282ms)
3. 1.35V (On board measured ripple 28mV and rise time of 1.651ms)
4. 1.025V Core Voltage (On board measured ripple 21.6mV and rise time 2.005ms)
I had gone through the datasheet of T2081 and there is no power supply sequencing. Is there any power supply architecture specific to T2081 available? I was referring the T2080 evaluation module where Infineon power supply regulators are used. All the regulators have already reached EoL. Can you suggest any other regulators which are still in production for all the power supplies?
Also can you once review our design and let us know if because of design issue or layout issue we are finding the current issues cropping on the boards.
Power sequencing: QorIQ T2081 Data Sheet, 3.2 Power sequencing
There are no specific recommendations for the EOL power supplies because these are not NXP parts.
Design review is possible by request of a FAE.